# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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© 2005-2011 Microchip Technology Inc. DS70157F-page 175
Section 5. Instruction Descriptions
Instruction
Descriptions
5
BTSTS
Bit Test/Set in Ws
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} BTSTS.C Ws, #bit4
BTSTS.Z [Ws],
[Ws++],
[Ws--],
[++Ws],
[--Ws],
Operands: Ws ∈ [W0 ... W15]
bit4 ∈ [0 ... 15]
Operation: For “.C” operation:
(Ws)<bit4> →C
1 → Ws<bit4>
For “.Z” operation (default):
(Ws)<bit4> → Z
1 → Ws<bit4>
Status Affected: Z or C
Encoding: 1010 0100 bbbb Z000 0ppp ssss
Description: Bit ‘bit4’ in register Ws is tested. If the “.Z” option of the instruction is
specified, the complement of the tested bit is stored to the Zero flag in the
STATUS register. If the “.C” option of the instruction is specified, the value
of the tested bit is stored to the Carry flag in the STATUS register. In both
cases, the tested bit in Ws is set to ‘1’.
The ‘b’ bits select the value bit4, the bit position to test/set.
The ‘Z’ bit selects the C or Z flag as destination.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note 1: This instruction only operates in Word mode. If no extension is
provided, the “.Z” operation is assumed.
2: If Ws is used as a pointer, it must not contain the address of the
CPU Status register (SR).
3: In dsPIC33E and PIC24E devices, this instruction uses the
DSRPAG register for indirect address generation in Extended
Data Space.
Words: 1
Cycles:
1
(1)
Note 1:
In dsPIC33E and PIC24E devices, the listed cycle count does not apply to read and
read-modify-write operations on non-CPU Special Function Registers. For more
details, see
Note 3
in
Section 3.2.1 “Multi-Cycle Instructions”
.

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