# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA0XX -- Flash Programming Specification

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© 2008 Microchip Technology Inc. DS39768D-page 49
PIC24FJXXXGA0XX
7.0 AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS
Standard Operating Conditions
Operating Temperature: 0°C to +70°C. Programming at +25°C is recommended.
Param
No.
Symbol Characteristic Min Max Units Conditions
D111 V
DD Supply Voltage During Programming VDDCORE + 0.1 3.60 V Normal programming
(1,2)
D112 I PP Programming Current on MCLR — 5 μA
D113 I
DDP Supply Current During Programming — 2 mA
D031 V
IL Input Low Voltage VSS 0.2 VDD V
D041 V
IH Input High Voltage 0.8 VDD VDD V
D080 V
OL Output Low Voltage — 0.4 V IOL = 8.5 mA @ 3.6V
D090 V
OH Output High Voltage 3.0 — V IOH = -3.0 mA @ 3.6V
D012 C
IO Capacitive Loading on I/O pin (PGDx) — 50 pF To meet AC specifications
D013 C
F Filter Capacitor Value on VCAP 4.7 10 μF Required for controller core
P1 T
PGC Serial Clock (PGCx) Period 100 — ns
P1A T
PGCL Serial Clock (PGCx) Low Time 40 — ns
P1B T
PGCH Serial Clock (PGCx) High Time 40 — ns
P2 T
SET1 Input Data Setup Time to Serial Clock ↑ 15 — ns
P3 T
HLD1 Input Data Hold Time from PGCx ↑ 15 — ns
P4 T
DLY1 Delay Between 4-Bit Command and
Command Operand
40 — ns
P4A T
DLY 1A Delay Between 4-Bit Command Operand
and Next 4-Bit Command
40 — ns
P5 T
DLY2 Delay Between Last PGCx ↓ of Command
Byte to First PGCx ↑ of Read of Data Word
20 — ns
P6 T SET2 VDD ↑ Setup Time to MCLR ↑ 100 — ns
P7 T
HLD2 Input Data Hold Time from MCLR ↑ 25 — ms
P8 T
DLY3 Delay Between Last PGCx ↓ of Command
Byte to PGDx ↑ by Programming Executive
12 — μs
P9 T
DLY4 Programming Executive Command
Processing Time
40 — μs
P10 T
DLY6 PGCx Low Time After Programming 400 — ns
P11 T
DLY7 Chip Erase Time 400 — ms
P12 T
DLY8 Page Erase Time 40 — ms
P13 T
DLY9 Row Programming Time 2 — ms
P14 T
R MCLR Rise Time to Enter ICSP™ mode — 1.0 μs
P15 T
VALID Data Out Valid from PGCx ↑ 10 — ns
P16 T
DLY10 Delay Between Last PGCx ↓ and MCLR ↓ 0 — s
P17 T
HLD3 MCLR ↓ to VDD ↓ 100 — ns
P18 T
KEY1 Delay from First MCLR ↓ to First PGCx ↑
for Key Sequence on PGDx
40 — ns
P19 T
KEY2 Delay from Last PGCx ↓ for Key
Sequence on PGDx to Second MCLR
↑
1 — ms
P20 T
DLY11 Delay Between PGDx ↓ by Programming
Executive to PGDx Driven by Host
23 — µs
P21 T
DLY12 Delay Between Programming Executive
Command Response Words
8 — ns
Note 1: V
DDCORE must be supplied to the VDDCORE/V CAP pin if the on-chip voltage regulator is disabled. See Section 2.1
“Power Requirements” for more information. (Minimum V
DDCORE allowing Flash programming is 2.25V.)
2: V
DD must also be supplied to the AV DD pins during programming. AV DD and AV SS should always be within ±0.3V
of V
DD and VSS, respectively.

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