# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Family Data Sheet

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© 2011-2012 Microchip Technology Inc. Preliminary DS39997C-page 209
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
REGISTER 20-1: CMSTAT: COMPARATOR STATUS REGISTER
R/W-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0
CMSIDL — — — — C3EVT C2EVT C1EVT
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0
— — — — — C3OUT C2OUT C1OUT
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CMSIDL: Stop in Idle Mode bit
1 = Discontinue operation of all comparators when device enters Idle mode
0 = Continue operation of all comparators in Idle mode
bit 14-11 Unimplemented: Read as ‘0’
bit 10 C3EVT: Comparator 3 Event Status bit
1 = Comparator event occurred
0 = Comparator event did not occur
bit 9 C2EVT: Comparator 2 Event Status bit
1 = Comparator event occurred
0 = Comparator event did not occur
bit 8 C1EVT: Comparator 1 Event Status bit
1 = Comparator event occurred
0 = Comparator event did not occur
bit 7-3 Unimplemented: Read as ‘0’
bit 2 C3OUT: Comparator 3 Output Status bit
When CPOL =
0:
1 = VIN+ > V IN-
0 = V
IN+ < VIN-
When CPOL =
1:
1 = VIN+ < V IN-
0 = V
IN+ > VIN-
bit 1 C2OUT: Comparator 2 Output Status bit
When CPOL =
0:
1 = VIN+ > V IN-
0 = V
IN+ < VIN-
When CPOL =
1:
1 = VIN+ < V IN-
0 = V
IN+ > VIN-
bit 0 C1OUT: Comparator 1 Output Status bit
When CPOL =
0:
1 = VIN+ > V IN-
0 = V
IN+ < VIN-
When CPOL =
1:
1 = VIN+ < V IN-
0 = V
IN+ > VIN-

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