# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- CPU

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PIC24F Family Reference Manual
DS39703A-page 2-10 Advance Information © 2006 Microchip Technology Inc.
2.4 CPU REGISTER DESCRIPTIONS
2.4.1 SR: CPU STATUS Register
The PIC24F CPU has a 16-bit STATUS register (SR), the LSB of which is referred to as the lower
STATUS register (SRL). The upper byte of SR is referred to as SRH. A detailed description of SR
is shown in Register 2-1.
SRL contains all the MCU ALU operation Status flags, plus the CPU Interrupt Priority Level
Status bits, IPL<2:0>, and the REPEAT Loop Active Status bit, RA (SR<4>). During exception
processing, SRL is concatenated with the MSB of the PC to form a complete word value which
is then stacked.
SRH contains only the Digit Carry bit, DC (SR<8>).
The SR bits are readable/writable with the following exceptions:
1. The RA bit (SR<4>): RA is a read-only bit.
2. IPL<2:0>: When register is disabled (NSTDIS = 1), IPL<2:0> bits become read-only.
Note: A description of the SR bits affected by each instruction is provided in the
“dsPIC30F
Programmer’s Reference Manual”
(DS70030).

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