# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Serial Peripheral Interface

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© 2007 Microchip Technology Inc. Advance Information DS39699B-page 23-22
Section 23. Serial Peripheral Interface (SPI)
Serial Peripheral
Interface (SPI)
23
23.3.4.5 SPI SLAVE MODE AND FRAME MASTER MODE
In Slave/Frame Master mode, the module acts as the SPI slave and takes its clock from the other
SPI module; however, it produces frame synchronization signals to control data transmission
(Figure 23-15). It is enabled by setting the MSTEN bit to ‘0’, the FRMEN bit to ‘1’ and the SPIFSD
bit to ‘0’.
The input SPIx clock will be continuous in Slave mode. The SSx
pin will be an output when the
SPIFSD bit is low. Therefore, when the SPIxBUF is written, the module drives the SSx
pin to the
active state on the appropriate transmit edge of the SPIx clock for one SPIx clock cycle. Data will
start transmitting on the appropriate SPIx clock transmit edge.
Figure 23-15: SPI Slave, Frame Master Connection Diagram
23.3.4.6 SPI SLAVE MODE AND FRAME SLAVE MODE
In Slave/Frame Slave mode, the module obtains both its clock and frame synchronization signal
from the master module (Figure 23-16). It is enabled by setting MSTEN to ‘0’, FRMEN to ‘1’ and
SPIFSD to ‘1’.
In this mode, both the SCKx and SSx
pins will be inputs. The SSx pin is sampled on the sample
edge of the SPIx clock. When SSx
is sampled at its active state, data will be transmitted on the
appropriate transmit edge of SCKx.
Figure 23-16: SPI Slave, Frame Slave Connection Diagram
SDOx
SDIx
PIC24F
Serial Clock
SSx
SCKx
Frame Sync.
Pulse
SDIx
SDOx
PROCESSOR 2
SSx
SCKx
(SPI Slave, Frame Slave)
SDOx
SDIx
PIC24F
Serial Clock
SSx
SCKx
Frame Sync.
Pulse
SDIx
SDOx
PROCESSOR 2
SSx
SCKx
(SPI Master, Frame Slave)

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