# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Oscillator

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PIC24F Family Reference Manual
DS39700C-page 6-26 © 2009 Microchip Technology Inc.
6.11.2 Oscillator Switching Sequence
At a minimum, performing a clock switch requires this basic sequence:
1. If desired, read the COSC bits (OSCCON<14:12>) to determine the current oscillator
source.
2. Perform the unlock sequence to allow a write to the OSCCON register high byte.
3. Write the appropriate value to the NOSC control bits (OSCCON<10:8>) for the new
oscillator source.
4. Perform the unlock sequence to allow a write to the OSCCON register low byte.
5. Set the OSWEN bit to initiate the oscillator switch.
Once the basic sequence is completed, the system clock hardware responds automatically as
follows:
1. The clock switching hardware compares the COSC status bits with the new value of the
NOSC control bits. If they are the same, then the clock switch is a redundant operation.
In this case, the OSWEN bit is cleared automatically and the clock switch is aborted.
2. If a valid clock switch has been initiated, the LOCK (OSCCON<5>) and CF
(OSCCON<3>) status bits are cleared.
3. The new oscillator is turned on by the hardware if it is not currently running. If a crystal
oscillator must be turned on, the hardware will wait until the OST expires. If the new
source is using the PLL, then the hardware waits until a PLL lock is detected (LOCK = 1).
4. The hardware waits for the new clock source to stabilize and then performs the clock
switch.
5. The hardware clears the OSWEN bit to indicate a successful clock transition. In addition,
the NOSC bit values are transferred to the COSC status bits.
6. The old clock source is turned off at this time, with the exception of LPRC (if WDT or
FSCM is enabled) or SOSC (if SOSCEN remains set).
The timing of the transition between clock sources in shown in Figure 6-9.
Figure 6-9: Clock Transition Timing Diagram
Note: The processor will continue to execute code throughout the clock switching
sequence. Timing-sensitive code should not be executed during this time.
Old Clock Source
New Clock Source
System Clock
Both Oscillators Active
OSWEN bit
New Source
Enabled
New Source
Stable
Old Source
Disabled
Note: The system clock can be any selected source (Primary, Secondary, FRC or LPRC).

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