# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Family Data Sheet

- 1
- 2
…
- 160
- 161
- 162
- 163
- 164
…
- 349
- 350

PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
DS39997C-page 162 Preliminary © 2011-2012 Microchip Technology Inc.
REGISTER 15-5: PWMxCON1: PWM CONTROL REGISTER 1
(1)
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — PMOD3 PMOD2 PMOD1
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
— PEN3H
(2)
PEN2H
(2)
PEN1H
(2)
— PEN3L
(2)
PEN2L
(2)
PEN1L
(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10-8 PMOD3:PMOD1: PWM I/O Pair Mode bits
1 = PWM I/O pin pair is in the Independent PWM Output mode
0 = PWM I/O pin pair is in the Complementary Output mode
bit 7 Unimplemented: Read as ‘0’
bit 6-4 PEN3H:PEN1H: PWMxH I/O Enable bits
1 = PWMxH pin is enabled for PWM output
0 = PWMxH pin disabled, I/O pin becomes general purpose I/O
bit 3 Unimplemented: Read as ‘0’
bit 2-0 PEN3L:PEN1L: PWMxL I/O Enable bits
1 = PWMxL pin is enabled for PWM output
0 = PWMxL pin disabled, I/O pin becomes general purpose I/O
Note 1: The PWMxCON1 register is a write-protected register. Refer to Section 15.3 “Write-protected
Registers” for more information on the unlock sequence.
2: The reset status for this bit depends on the setting of the PWMPIN Configuration bit (FPOR<7>):
• If PWMPIN = 1 (default), the PWM pins are controlled by the PORT register at Reset, meaning they
are initially programmed as inputs (i.e., tri-stated).
• If PWMPIN = 0, the PWM pins are controlled by the PWM module at Reset and are therefore initially
programmed as output pins.

- 1
- 2
…
- 160
- 161
- 162
- 163
- 164
…
- 349
- 350