# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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dsPIC33/PIC24 Family Reference Manual
DS70000195F-page 18  2007-2014 Microchip Technology Inc.
4.0 ENABLING I
2
C OPERATION
The I
2
C module is enabled by setting the I2CEN bit (I2CxCON<15> or I2CxCONL<15>). The I
2
C
module fully implements all master and slave functions. When the module is enabled, the master
and slave functions are active simultaneously and will respond according to the user software or
bus events.
When initially enabled, the module will release the SDAx and SCLx pins, putting the bus into an
Idle state. The master functions will remain in an Idle state unless the user software sets the SEN
control bit and the data is loaded into the I2CxTRN register. These two actions initiate a master
event.
When the master logic is active, the slave logic also remains active. Therefore, the slave
functions will begin to monitor the bus. If the slave logic detects a Start event and a valid address
on the bus, the slave logic will begin a slave transaction.
4.1 I
2
C I/O Pins
Two pins are used for the bus operation. These are the SCLx pin, which is the clock, and the
SDAx pin, which is the data. When the module is enabled, assuming no other module with higher
priority has control, the module will assume control of the SDAx and SCLx pins. The user
software need not be concerned with the state of the port I/O of the pins, as the module overrides
the port state and direction. At initialization, the pins are tri-stated (released).
4.2 I
2
C Interrupts
The I
2
C module generates three interrupts: MI2CxIF, SI2CxIF and I2CxBCIF. The MI2CxIF
interrupt is assigned to the master events, the SI2CxIF interrupt is assigned to the slave events
and the I2CxBCIF is assigned for the bus collision interrupt. These interrupts set a corresponding
interrupt flag bit and interrupt the user software process if the corresponding interrupt enable bit
is set, and the corresponding interrupt priority is higher than the CPU interrupt priority.
The MI2CxIF interrupt is generated on completion of the following master message events:
• Start condition
• Stop condition
• Data transfer byte transmitted or received
• Acknowledge transmit
• Repeated Start
• Detection of a bus collision event.
The SI2CxIF interrupt is generated on detection of a message directed to the slave, including the
following events:
• Detection of a Start condition (see Note 1)
• Detection of a Stop condition (see Note 1)
• Detection of a Repeated Start condition (see Note 1)
• Detection of a valid device address (including general call) during receiving data
• Request to transmit the data (ACK
) or to stop the data transmission (NACK)
• Reception of data
The I2CxBCIF interrupt is generated on a bus collision event in master/slave transmit operation:
• Start condition (master)
• Stop condition (master)
• Repeated Start (master)
• Data (master and slave)
• Acknowledge transmit (master and slave)
Note: In some devices, the bus collision interrupt is not tied with the MI2CxIF interrupt.
Note 1: These interrupts may not be present on all devices. Refer to the specific device
data sheet for availability.

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