# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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 2007-2014 Microchip Technology Inc. DS70000195F-page 49
Inter-Integrated Circuit™ (I
2
C™)
7.3.11 ADDRESSES RESERVED FROM MASKING
Even when enabled, there are several addresses that are ignored by the I
2
C module. For these
addresses, an Acknowledge will not be issued independent of the mask setting. These
addresses are listed in Table 7-2.
Table 7-2: Reserved I
2
C™ Bus Addresses
(3)
7.4 Receiving Data from a Master Device
When the R/W status bit of the device address byte is ‘0’ and an address match occurs, the R/W
status bit (I2CxSTAT<2>) is cleared. The slave enters a state waiting for data to be sent by the
master. After the device address byte, the contents of the data byte are defined by the system
protocol and are only received by the slave.
The slave shifts 8 bits into the I2CxRSR register. On the falling edge of the eighth clock (SCLx),
the following events occur:
• The module begins to generate an ACK
or NACK.
• The RBF status bit (I2CxSTAT<1>) is set to indicate received data.
• The I2CxRSR register byte is transferred to the I2CxRCV register for access by the user
software.
• The D/A
status bit is set.
• A slave interrupt is generated. User software can check the status of the I2CxSTAT register
to determine the cause of the event and then clear the SI2CxIF interrupt flag.
• The module waits for the next data byte.
7-Bit Address Mode
Slave Address R/W
Bit Description
0000 000 0 General Call Address
(1)
0000 000 1 Start Byte
0000 001 x Cbus Address
0000 010 x Reserved
0000 011 x Reserved
0000 1xx x HS Mode Master Code
1111 1xx x Reserved
1111 0xx x 10-Bit Slave Upper Byte
(2)
Note 1: Address will be Acknowledged only if GCEN = 1.
2: A match on this address can only occur as the upper byte in 10-Bit Addressing mode.
3: These addresses will not be Acknowledged, independent of mask settings and
STRICT = 1.

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