# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

- 1
- 2
…
- 167
- 168
- 169
- 170
- 171
…
- 501
- 502

© 2005-2011 Microchip Technology Inc. DS70157F-page 169
Section 5. Instruction Descriptions
Instruction
Descriptions
5
BTST
Bit Test in Ws
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} BTST.C Ws, #bit4
BTST.Z [Ws],
[Ws++],
[Ws--],
[++Ws],
[--Ws],
Operands: Ws ∈ [W0 ... W15]
bit4 ∈ [0 ... 15]
Operation: For “.C” operation:
(Ws)<bit4> → C
For “.Z” operation (default):
(Ws)<bit4> → Z
Status Affected: Z or C
Encoding: 1010 0011 bbbb Z000 0ppp ssss
Description: Bit ‘bit4’ in register Ws is tested. If the “.Z” option of the instruction is
specified, the complement of the tested bit is stored to the Zero flag in the
STATUS register. If the “.C” option of the instruction is specified, the value
of the tested bit is stored to the Carry flag in the STATUS register. In either
case, the contents of Ws are not changed.
For the bit4 operand, bit numbering begins with the Least Significant bit
(bit 0) and advances to the Most Significant bit (bit 15) of the word. Either
register direct or indirect addressing may be used for Ws.
The ‘b’ bits select value bit4, the bit position to test.
The ‘Z’ bit selects the C or Z flag as destination.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note: This instruction only operates in Word mode. If no extension is
provided, the “.Z” operation is assumed.
Words: 1
Cycles:
1
(1)
Note 1:
In dsPIC33E and PIC24E devices, the listed cycle count does not apply to read and
read-modify-write operations on non-CPU Special Function Registers. For more
details, see
Note 3
in
Section 3.2.1 “Multi-Cycle Instructions”
.

- 1
- 2
…
- 167
- 168
- 169
- 170
- 171
…
- 501
- 502