# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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© 2005-2011 Microchip Technology Inc. DS70157F-page 173
Section 5. Instruction Descriptions
Instruction
Descriptions
5
BTSTS
Bit Test/Set f
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} BTSTS{.B} f, #bit4
Operands: f ∈ [0 ... 8191] for byte operation
f ∈ [0 ... 8190] (even only) for word operation
bit4 ∈ [0 ... 7] for byte operation
bit4 ∈ [0 ... 15] for word operation
Operation: (f)<
bit4> → Z
1 → (f)<bit4>
Status Affected: Z
Encoding: 1010 1100 bbbf ffff ffff fffb
Description: Bit ‘bit4’ in file register ‘f’ is tested and the complement of the tested bit is
stored to the Zero flag in the STATUS register. The tested bit is then set
to ‘1’ in the file register. For the bit4 operand, bit numbering begins with
the Least Significant bit (bit 0) and advances to the Most Significant bit
(bit 7 for byte operations, bit 15 for word operations).
The ‘b’ bits select value bit4, the bit position to test/set.
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: When this instruction operates in Word mode, the file register
address must be word-aligned.
3: When this instruction operates in Byte mode, ‘bit4’ must be
between 0 and 7.
4: The file register ‘f’ must not be the CPU Status register (SR).
Words: 1
Cycles:
1
(1)
Note 1:
In dsPIC33E and PIC24E devices, the listed cycle count does not apply to read and
read-modify-write operations on non-CPU Special Function Registers. For more
details, see
Note 3
in
Section 3.2.1 “Multi-Cycle Instructions”
.

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