# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Oscillator

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© 2009 Microchip Technology Inc. DS39700C-page 6-25
Section 6. Oscillator
Oscillator
6
6.10.3 FSCM and WDT
The FSCM and the WDT both use the LPRC Oscillator as their time base. In the event of a clock
failure, the WDT is unaffected and continues to run on the LPRC.
6.11 CLOCK SWITCHING OPERATION
With few limitations, applications are free to switch between any of the four clock sources
(Primary, SOSC, FRC and LPRC) under software control and at any time. To limit the possible
side effects that could result from this flexibility, PIC24F devices have a safeguard lock built into
the switch process.
6.11.1 Enabling Clock Switching
To enable clock switching, the FCKSM1 Configuration bit must be programmed to ‘0’. (Refer to
the specific device data sheet for further details.) If the FCKSM1 Configuration bit is unpro-
grammed (‘1’), the clock switching function and Fail-Safe Clock Monitor function are disabled.
This is the default setting.
The NOSC control bits (OSCCON<10:8>) do not control the clock selection when clock switching
is disabled. However, the COSC bits (OSCCON<14:12>) will reflect the clock source selected by
the FNOSC Configuration bits.
The OSWEN control bit (OSCCON<0>) has no effect when clock switching is disabled; it is held
at ‘0’ at all times.
Note: Primary Oscillator mode has three different submodes (XT, HS and EC), which are
determined by the POSCMD Configuration bits. While an application can switch to
and from Primary Oscillator mode in software, it cannot switch between the different
primary submodes without reprogramming the device.

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