# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Motor Control PWM

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PIC24F Family Reference Manual
DS39735A-page 47-24 Preliminary © 2010 Microchip Technology Inc.
47.8 TIME BASE INTERRUPTS
The generation of PWM interrupts depends on the mode of operation selected by the PWM
Time Base Mode Select (PTMOD) bits of the PWM Time Base Control (PxTCON<1:0>)
register and the time base output postscaler selected using the PWM Time Base Output
Postscale Select (PTOPS) bits of the PxTCON register (PxTCON<7:4>).
The interrupt generation for each of the operating modes is described in the following four
sections.
47.8.1 Free-Running Mode
An interrupt event is generated when the PWM Time Base (PxTMR) register is reset to zero
due to a match with the PWM Time Base Period (PxTPER) register. The postscaler selection
bits can be used in Free-Running mode to reduce the frequency of the interrupt events.
47.8.2 Single Event Mode
An interrupt event is generated when the PxTMR register is reset to zero due to a match with
the PxTPER register. The PWM Time Base Timer Enable (PTEN) bit of the PxTCON register
(PxTCON<15>) is also cleared to inhibit further PxTMR increments. The postscaler selection
bits have no effect in Single Event mode.
47.8.3 Up/Down Counting Mode
An interrupt event is generated each time the value of the PxTMR register is equal to zero and
the PWM time base begins to count upward. The postscale selection can be used to reduce
the frequency of interrupt events in Up/Down Counting mode.
47.8.4 Up/Down Counting Mode with Double Update of Duty Cycle
An interrupt event is generated each time the PxTMR register is equal to zero and each time a
period match occurs. The postscale selection has no effect in Up/Down Counting mode with
Double Update of Duty Cycle. This mode allows the control loop bandwidth to be doubled
because the PWM duty cycles can be updated twice per period. Every rising and falling edge
of the PWM signal can be controlled using the Double Update mode.
On generation of a PWM interrupt, the PWM Interrupt Flag, PWMIF, is set in the corresponding
IFS register.

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