# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004

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PIC24FJ64GA004 FAMILY
DS39881E-page 178  2010-2013 Microchip Technology Inc.
19.1 RTCC Module Registers
The RTCC module registers are organized into three
categories:
 RTCC Control Registers
 RTCC Value Registers
 Alarm Value Registers
19.1.1 REGISTER MAPPING
To limit the register interface, the RTCC Timer and Alarm
Time registers are accessed through corresponding reg-
ister pointers. The RTCC Value register window
(RTCVALH and RTCVALL) uses the RTCPTR<1:0> bits
(RCFGCAL<9:8>) to select the desired Timer register
pair (see Table 19-1).
By writing the RTCVALH byte, the RTCC Pointer value
(the RTCPTR<1:0> bits) decrements by one until the
bits reach 00. Once they reach 00, the MINUTES
and SECONDS value will be accessible through
RTCVALH and RTCVALL until the pointer value is
manually changed.
TABLE 19-1: RTCVAL REGISTER MAPPING
The Alarm Value register window (ALRMVALH and
ALRMVALL) uses the ALRMPTR bits (ALCFGRPT<9:8>)
to select the desired Alarm register pair (see Table 19-2).
By writing the ALRMVALH byte, the Alarm Pointer
value (the ALRMPTR<1:0> bits) decrements by one
until the bits reach 00. Once they reach 00, the
ALRMMIN and ALRMSEC value will be accessible
through ALRMVALH and ALRMVALL until the pointer
value is manually changed.
TABLE 19-2: ALRMVAL REGISTER
MAPPING
Considering that the 16-bit core does not distinguish
between 8-bit and 16-bit read operations, the user must
be aware that when reading either the ALRMVALH
or ALRMVALL, the bytes will decrement the
ALRMPTR<1:0> value. The same applies to the
RTCVALH or RTCVALL bytes with the RTCPTR<1:0>
being decremented.
19.1.2 WRITE LOCK
In order to perform a write to any of the RTCC Timer
registers, the RTCWREN bit (RCFGCAL<13>) must be
set (refer to Example 19-1).
EXAMPLE 19-1: SETTING THE RTCWREN BIT
RTCPTR
<1:0>
RTCC Value Register Window
RTCVAL<15:8> RTCVAL<7:0>
00 MINUTES SECONDS
01 WEEKDAY HOURS
10 MONTH DAY
11  YEAR
ALRMPTR
<1:0>
Alarm Value Register Window
ALRMVAL<15:8> ALRMVAL<7:0>
00 ALRMMIN ALRMSEC
01 ALRMWD ALRMHR
10 ALRMMNTH ALRMDAY
11  
Note: This only applies to read operations and
not write operations.
Note: To avoid accidental writes to the timer, it is
recommended that the RTCWREN bit
(RCFGCAL<13>) is kept clear at any
other time. For the RTCWREN bit to be
set, there is only 1 instruction cycle time
window allowed between the 55h/AA
sequence and the setting of RTCWREN;
therefore, it is recommended that code
follow the procedure in Example 19-1.
asm volatile("push w7");
asm volatile("push w8");
asm volatile("disi #5");
asm volatile("mov #0x55, w7");
asm volatile("mov w7, _NVMKEY");
asm volatile("mov #0xAA, w8");
asm volatile("mov w8, _NVMKEY");
asm volatile("bset _RCFGCAL, #13"); //set the RTCWREN bit
asm volatile("pop w8");
asm volatile("pop w7");

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