# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004

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PIC24FJ64GA004 FAMILY
DS39881E-page 62  2010-2013 Microchip Technology Inc.
7.3 Interrupt Control and Status
Registers
The PIC24FJ64GA004 family of devices implements a
total of 29 registers for the interrupt controller:
 INTCON1
 INTCON2
 IFS0 through IFS4
 IEC0 through IEC4
 IPC0 through IPC12, IPC15, IPC16 and IPC18
 INTTREG
Global interrupt control functions are controlled from
INTCON1 and INTCON2. INTCON1 contains the Inter-
rupt Nesting Disable (NSTDIS) bit, as well as the
control and status flags for the processor trap sources.
The INTCON2 register controls the external interrupt
request signal behavior and the use of the Alternate
Interrupt Vector Table.
The IFSx registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit which is
set by the respective peripherals, or external signal,
and is cleared via software.
The IECx registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.
The IPCx registers are used to set the Interrupt Priority
Level (IPL) for each source of interrupt. Each user
interrupt source can be assigned to one of eight priority
levels.
The INTTREG register contains the associated inter-
rupt vector number and the new CPU Interrupt Priority
Level, which are latched into the Vector Number
(VECNUM<6:0>) and the Interrupt Level (ILR<3:0>) bit
fields in the INTTREG register. The new Interrupt
Priority Level is the priority of the pending interrupt.
The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence that they are
listed in Table 7-2. For example, the INT0 (External
Interrupt 0) is shown as having a vector number and a
natural order priority of 0. Thus, the INT0IF status bit is
found in IFS0<0>, the INT0IE enable bit in IEC0<0>
and the INT0IP<2:0> priority bits in the first position of
IPC0 (IPC0<2:0>).
Although they are not specifically part of the interrupt
control hardware, two of the CPU control registers con-
tain bits that control interrupt functionality. The ALU
STATUS Register (SR) contains the IPL<2:0> bits
(SR<7:5>). These indicate the current CPU Interrupt
Priority Level. The user may change the current CPU
priority level by writing to the IPLx bits.
The CORCON register contains the IPL3 bit, which
together with IPL<2:0>, also indicates the current CPU
priority level. IPL3 is a read-only bit so that trap events
cannot be masked by the user software.
All Interrupt registers are described in Register 7-1
through Register 7-31, in the following pages.

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