# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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dsPIC33/PIC24 Family Reference Manual
DS70000195F-page 4  2007-2014 Microchip Technology Inc.
2.0 I
2
C BUS CHARACTERISTICS
The I
2
C bus is a 2-wire serial interface. Figure 2-1 illustrates the schematic of an I
2
C connection
between a dsPIC33/PIC24 device and a 24LC256 I
2
C serial EEPROM, which is a typical
example for any I
2
C interface.
The I
2
C interface uses a comprehensive protocol to ensure reliable transmission and reception
of the data. When communicating, one device acts as the “master” and it initiates transfer on the
bus, and generates the clock signals to permit that transfer, while the other devices act as the
“slave” responding to the transfer. The clock line, SCLx, is output from the master and input to
the slave, although occasionally the slave drives the SCLx line. The data line, SDAx, may be
output and input from both the master and slave.
Because the SDAx and SCLx lines are bidirectional, the output stages of the devices driving the
SDAx and SCLx lines must have an open-drain in order to perform the wired-AND function of the bus.
External pull-up resistors are used to ensure a high level when no device is pulling the line down.
In the I
2
C interface protocol, each device has an address. When a master needs to initiate a data
transfer, it first transmits the address of the device that it wants to “communicate”. All of the
devices “listen” to see if this is their address. Within this address, bit 0 specifies whether the
master wants to read from or write to the slave device. The master and slave are always in
opposite modes (Transmitter or Receiver) of operation during a data transfer. That is, they
operate in either of the following two relations:
• Master-Transmitter and Slave-Receiver
• Slave-Transmitter and Master-Receiver
In both cases, the master originates the SCLx clock signal.
Figure 2-1: Typical I
2
C™ Interconnection Block Diagram
SCLx
SDAx
dsPIC33/PIC24
SDA
SCL
VDD VDD
2.2 k
24LC256
(typical)

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