# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- 10-Bit ADC

- 1
- 2
…
- 46
- 47
- 48
- 49
- 50
…
- 57
- 58

PIC24F Family Reference Manual
DS39737A-page 49-48 Preliminary © 2010 Microchip Technology Inc.
49.10 A/D SAMPLING REQUIREMENTS
The analog input model of the 10-bit ADC model is shown in Figure 49-25. The total sampling
time for the A/D conversion is a function of the internal amplifier settling time and the holding
capacitor charge time.
For the ADC module to meet its specified accuracy, the charge holding capacitor (C
HOLD) must
be allowed to fully charge to the voltage level on the analog input pin. The analog output source
impedance (R S), the interconnect impedance (RIC) and the internal sampling switch (RSS)
impedance combine to directly affect the time required to charge the capacitor C
HOLD. The
combined impedance must, therefore, be small enough to fully charge the holding capacitor
within the chosen sample time. To minimize the effects of pin leakage currents on the accuracy
of the ADC module, the maximum recommended source impedance, R
S, which is 200. After
the analog input channel is selected, this sampling function must be completed prior to starting
the conversion. The internal holding capacitor will be in a discharged state prior to each sample
operation.
A minimum time period should be allowed between conversions for the sample time. For more
details about the minimum sampling time for a device, refer to the “Electrical Characteristics”
chapter of the specific device data sheet.
Figure 49-25: 10-Bit Analog Input Model
CPIN
(1)
VA
Rs
ANx
V
T = 0.6V
VT = 0.6V
I
LEAKAGE
RIC  250
Sampling
Switch
R
SS
CHOLD
= DAC capacitance
V
SS
VDD
= 4.4 pF
 500 nA
Legend: CPIN
VT
ILEAKAGE
RIC
RSS
CHOLD
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to
= Interconnect Resistance
= Sampling Switch Resistance
= S&H Capacitance (from DAC)
various junctions
Note 1: CPIN value depends on device package and is not tested. The effect of C PIN is negligible if Rs  500
R
SS  3 k

- 1
- 2
…
- 46
- 47
- 48
- 49
- 50
…
- 57
- 58