# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 86 © 2005-2011 Microchip Technology Inc.
If a prefetch is used in the instruction, the assembler is capable of discriminating between the X
or Y data prefetch based on the register used for the effective address. [W8] or [W9] specifies
the X prefetch and [W10] or [W11] specifies the Y prefetch. Brackets around the working register
are required in the syntax, and they designate that indirect addressing is used to perform the
prefetch. When address modification is used, it must be specified using a minus-equals or
plus-equals “C”-like syntax (i.e., “[W8] – = 2” or “[W8] + = 6”). When Register Offset Addressing
is used for the prefetch, W12 is placed inside the brackets ([W9 + W12] for X prefetches and [W11
+ W12] for Y prefetches). Each prefetch operation must also specify a prefetch destination
register (W4-W7). In the instruction syntax, the destination register appears before the prefetch
register. Legal forms of prefetch are shown in Example 4-20.
Example 4-20: MAC Prefetch Syntax
If an accumulator Write Back is used in the instruction, it is specified last. The Write Back must
use the W13 register, and allowable forms for the Write Back are “W13” for direct addressing and
“[W13] + = 2” for indirect addressing with post-increment. By definition, the accumulator not used
in the mathematical operation is stored, so the Write Back accumulator is not specified in the
instruction. Legal forms of accumulator Write Back (WB) are shown in
Example 4-21.
X([W8]+=2)→ W5
ACCA=ACCA+W5*W6
; MAC with X only prefetch
MAC W5*W6, A, [W8]+=2, W5
Y([W11+W12])→ W5
ACCB=ACCB+W5*W5
; MAC with Y only prefetch
MAC W5*W5, B, [W11+W12], W5
X([W9])→ W6
ACCB=ACCB+W6*W7
Y([W10]+=4)→W7
; MAC with X/Y prefetch
MAC W6*W7, B, [W9], W6, [W10]+=4, W7

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