# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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 2007-2014 Microchip Technology Inc. DS70000195F-page 27
Inter-Integrated Circuit™ (I
2
C™)
5.5 Generating a Stop Bus Event
Setting the PEN bit (I2CxCON<2> or I2CxCONL<2>), enables the generation of a master Stop
sequence.
When the PEN bit is set, the master generates the Stop sequence, as illustrated in Figure 5-7.
• The slave detects the Stop condition, sets the P status bit (I2CxSTAT<4>) and clears the
S status bit (I2CxSTAT<3>)
• The PEN bit is automatically cleared
• The module generates the MI2CxIF interrupt
5.5.1 IWCOL STATUS FLAG
If the user software writes the I2CxTRN register when a Stop sequence is in progress, the
IWCOL status bit (I2CxSTAT<7>) is set and the contents of the buffer are unchanged (the write
does not occur).
Figure 5-7: Master Stop Timing Diagram
Note: The lower 5 bits of the I2CxCON or I2CxCONL register must be ‘0’ (master logic
inactive) before attempting to set the PEN bit.
Note: Because queuing of events is not allowed, writing to the lower 5 bits of the I2CxCON
or I2CxCONL register is disabled until the Stop condition is complete.
SCLx (Master)
SDAx (Master)
S
PEN
MI2CxIF Interrupt
TBRG
1 2 3 5
Writing PEN = 1 initiates a master Stop event.
1
TBRG
BRG starts. Module drives SDAx low.
The BRG times out. Module releases SCLx.
2
BRG restarts.
The BRG times out. Module releases SDAx.
3
Slave logic detects a Stop. Module sets P = 1 and S = 0.
4
I
2
C™ Bus State
(I)
P
TBRG
(Q)
4
BRG restarts.
The BRG times out. Module clears PEN.
5
Master generates the interrupt.
(Q)
(P)

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