# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Motor Control PWM

- 1
- 2
…
- 30
- 31
- 32
- 33
- 34
…
- 49
- 50

PIC24F Family Reference Manual
DS39735A-page 47-32 Preliminary © 2010 Microchip Technology Inc.
The MCPWM module can produce PWM signal edges with T CY/2 resolution. PxTMR increments
every T
CY with a 1:1 prescaler. To achieve T CY/2 edge resolution, PxDC3:PxDC1<15:1> are
compared to PxTMR<14:0> to determine a duty cycle match. The value in PxDC3:PxDC1<0>
determines whether the PWM signal edge will occur at the T CY or the T CY/2 boundary. When a
1:4, 1:16 or 1:64 prescaler is used with the PWM time base, PxDC3:PxDC1<0> is compared to
the Most Significant bit (MSb) of the prescaler counter clock to determine when the PWM edge
should occur.
PxTMR and PxDC3:PxDC1 resolutions are depicted in Figure 47-15. In this example, PxTMR
resolution is T CY and PxDC3:PxDC1 resolution is T CY/2 for 1:1 prescaler selection.
Figure 47-15: PxTMR and PxDC3:PxDC1 Resolution Timing Diagram, Free-Running
Mode and 1:1 Prescaler Selection
Figure 47-16: Duty Cycle Comparison Logic
PxTPER = 10
PxTMR
PxDC3:PxDC1 = 14
PxDC3:PxDC1 = 15
T
CY
T CY
T CY/2
PxTMR N 2 1 T CY
15-Bit
Comparison
PxDC3:PxDC1
Edge
Logic
PWM Edge Event
14 0 N-Bit Prescaler
15
15 1 0
15
1-Bit Comparison
Note: PxDC3:PxDC1<0> is compared to the F OSC/2 signal when the prescaler is 1:1.

- 1
- 2
…
- 30
- 31
- 32
- 33
- 34
…
- 49
- 50