# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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© 2005-2011 Microchip Technology Inc. DS70157F-page 41
Section 3. Instruction Set Overview
Instruction Set
Overview
3
Table 3-3: Math Instructions
Assembly Syntax Description Words Cycles
Page
Number
ADD f {,WREG}
(1)
Destination = f + WREG 1 1
(5)
99
ADD #lit10,Wn Wn = lit10 + Wn 1 1 100
ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 101
ADD Wb,Ws,Wd Wd = Wb + Ws 1 1
(5)
102
ADDC f {,WREG}
(1)
Destination = f + WREG + (C) 1 1
(5)
106
ADDC #lit10,Wn Wn = lit10 + Wn + (C) 1 1 107
ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 108
ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1
(5)
110
DAW.B Wn Wn = decimal adjust Wn 1 1 216
DEC f {,WREG}
(1)
Destination = f – 1 1 1
(5)
217
DEC Ws,Wd Wd = Ws – 1 1 1
(5)
218
DEC2 f {,WREG}
(1)
Destination = f – 2 1 1
(5)
220
DEC2 Ws,Wd Wd = Ws – 2 1 1
(5)
221
DIV.S Wm, Wn Signed 16/16-bit integer divide, Q → W0, R → W1 1 18
(2)
224
DIV.SD Wm, Wn Signed 32/16-bit integer divide, Q → W0, R → W1 1 18
(2)
224
DIV.U Wm, Wn Unsigned 16/16-bit integer divide, Q - W0, R → W1 1 18
(2)
226
DIV.UD Wm, Wn Unsigned 32/16-bit integer divide, Q - W0, R → W1 1 18
(2)
226
DIVF Wm, Wn Signed 16/16-bit fractional divide, Q - W0, R → W1 1 18
(2)
228
INC f {,WREG}
(1)
Destination = f + 1 1 1
(5)
254
INC Ws,Wd Wd = Ws + 1 1 1
(5)
255
INC2 f {,WREG}
(1)
Destination = f + 2 1 1
(5)
257
INC2 Ws,Wd Wd = Ws + 2 1 1
(5)
258
MUL f W3:W2 = f * WREG 1 1
(5)
303
MUL.SS Wb,Ws,Wnd {Wnd + 1,Wnd} = signed(Wb) * signed(Ws) 1 1
(5)
305
MUL.SS Wb,Ws,Acc
(4)
Accumulator = signed(Wb) * signed(Ws) 1 1
(5)
307
MUL.SU Wb,#lit5,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5) 1 1 308
MUL.SU Wb,Ws,Wnd {Wnd + 1,Wnd} = signed(Wb) * unsigned(Ws) 1 1
(5)
310
MUL.SU Wb,Ws,Acc
(4)
Accumulator = signed(Wb) * unsigned(Ws) 1 1
(5)
312
MUL.SU Wb,#lit5,Acc
(4)
Accumulator = signed(Wb) * unsigned(lit5) 1 1 314
MUL.US Wb,Ws,Wnd {Wnd + 1,Wnd} = unsigned(Wb) * signed(Ws) 1 1
(5)
315
MUL.US Wb,Ws,Acc
(4)
Accumulator = unsigned(Wb) * signed(Ws) 1 1
(5)
317
MUL.UU Wb,#lit5,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * unsigned(lit5) 1 1 319
MUL.UU Wb,Ws,Wnd {Wnd + 1,Wnd} = unsigned(Wb) * unsigned(Ws) 1 1
(5)
320
MUL.UU Wb,Ws,Acc
(4)
Accumulator = unsigned(Wb) * unsigned(Ws) 1 1
(5)
322
MUL.UU Wb,#lit5,Acc
(4)
Accumulator = unsigned(Wb) * unsigned(lit5) 1 1 323
MULW.SS Wb,Ws,Wnd
(3)
Wnd = signed(Wb) * signed(Ws) 1 1
(5)
324
Note 1: When the optional {,WREG} operand is specified, the destination of the instruction is WREG. When
{,WREG} is not specified, the destination of the instruction is the file register f.
2: The divide instructions must be preceded with a “REPEAT #17” instruction, such that they are executed
18 consecutive times.
3: These instructions are only available in dsPIC33E and PIC24E devices.
4: These instructions are only available in dsPIC33E devices.
5: In dsPIC33E and PIC24E devices, read and read-modify-write operations on non-CPU Special Function
Registers require an additional cycle when compared to dsPIC30F, dsPIC33F, PIC24F and PIC24H
devices.

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