# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 -- Errata

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 2009-2013 Microchip Technology Inc. DS80000470H-page 11
PIC24FJ64GA004 FAMILY
22. Module: I/O Ports
During Power-on Reset (POR), the device may
drive the OSCO/RA3 pin as a clock out output for
approximately 20 S. During this time, the pin will
be driven high and low rather than being set to
high-impedance. This may cause issues on
designs that use the pin as a general purpose I/O.
Designs should be reviewed to ensure that their
intended operation will not be disrupted if the pin is
driven during POR.
Work around
None.
Affected Silicon Revisions
23. Module: JTAG
When entering the SHIFT_DR state while in
ICSP™ Communications mode, an extra clock
edge may be generated, causing JTAG and ICSP
communications to lose synchronization. This
prevents device programming using ICSP over
JTAG. JTAG boundary scan is not affected and
operates as expected.
Work around
None.
Affected Silicon Revisions
24. Module: RTCC
When performing writes to the ALCFGRPT regis-
ter, some bits may become corrupted. The error
occurs because of desynchronization between the
CPU clock domain and the RTCC clock domain.
The error causes data, from the instruction
following the ALCFGRPT instruction, to overwrite
the data in ALCFGRPT.
Work around
Always follow writes to the ALCFGRPT register
with an additional write of the same data to a
dummy location. These writes can be performed to
RAM locations, W registers or unimplemented
SFR space.
The optimal way to perform the work around:
1. Read ALCFGRPT into a RAM location.
2. Modify the ALCFGRPT data, as required, in
RAM.
3. Move the RAM value into ALCFGRPT and a
dummy location, in back-to-back instructions.
Affected Silicon Revisions
25. Module: I
2
C
When the I
2
C module is operating in Slave mode,
after the ACKSTAT bit is set when receiving a
NACK from the master, it may be cleared by the
reception of a Start or Stop bit.
Due to this issue, the state of ACKSTAT, after a
transmission finishes, will vary depending on the
device revision. On revisions with this issue,
ACKSTAT will be clear at the end of the transmis-
sion, and will remain clear until the next NACK is
received from the Master. On revisions without the
issue, ACKSTAT will be set at the end of a trans-
mission and will remain set until receiving an ACK
from the Master.
Work around
Store the value of the ACKSTAT bit immediately
after receiving a NACK from the master.
Affected Silicon Revisions
A3/
A4
B4 B5
B8
X
A3/
A4
B4 B5
B8
X
A3/
A4
B4 B5 B8
X
A3/
A4
B4 B5
B8
X

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