# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 -- UART

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dsPIC33/PIC24 Family Reference Manual
DS70000582E-page 22  2009-2013 Microchip Technology Inc.
7.3 Receive Interrupt
The UARTx Receive Interrupt Flag (UxRXIF) bit is located in the corresponding Interrupt Flag
Status x register (IFSx). The URXISEL<1:0> control bits (UxSTA<7:6>) determine when the
UART receiver generates an interrupt.
 If URXISEL<1:0> = 00 or 01, an interrupt is generated each time a data word is transferred
from the UARTx Receive Shift Register (UxRSR) to the receive buffer. There may be one or
more characters in the receive buffer.
 If URXISEL<1:0> = 10, an interrupt is generated when a word is transferred from the
UxRSR register to the receive buffer, and as a result, the receive buffer contains three or
four characters.
 If URXISEL<1:0> = 11, an interrupt is generated when a word is transferred from the
UxRSR register to the receive buffer, and as a result, the receive buffer contains four
characters (i.e., becomes full).
Switching between the three Interrupt modes during operation is possible.
While the URXDA and UxRXIF flag bits indicate the status of the UxRXREG register, the RIDLE
bit (UxSTA<4>) shows the status of the UxRSR register. The RIDLE status bit is a read-only bit
and is set when the receiver is Idle (i.e., the UxRSR register is empty). No interrupt logic is tied
to this bit, so the user application needs to poll this bit in order to determine if the UxRSR register
is Idle.
The URXDA bit (UxSTA<0>) is a read-only bit, which indicates whether the receive buffer has
data or is empty. This bit is set as long as there is at least one character to be read from the
receive buffer.
Figure 7-1 illustrates a block diagram of the UART receiver.

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