# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Family Data Sheet

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© 2011-2012 Microchip Technology Inc. Preliminary DS39997C-page 37
TABLE 4-1: CPU CORE REGISTERS MAP
SFR Name
SFR
Addr
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B
WREG0 0000 Working Register 0
WREG1 0002 Working Register 1
WREG2 0004 Working Register 2
WREG3 0006 Working Register 3
WREG4 0008 Working Register 4
WREG5 000A Working Register 5
WREG6 000C Working Register 6
WREG7 000E Working Register 7
WREG8 0010 Working Register 8
WREG9 0012 Working Register 9
WREG10 0014 Working Register 10
WREG11 0016 Working Register 11
WREG12 0018 Working Register 12
WREG13 001A Working Register 13
WREG14 001C Working Register 14
WREG15 001E Working Register 15
SPLIM 0020 Stack Pointer Limit Register
PCL 002E Program Counter Low Word Register
PCH 0030 — — — — — — — — Program Counter High Byte Regis
TBLPAG 0032 — — — — — — — — Table Page Address Pointer Register
PSVPAG 0034 — — — — — — — — Program Memory Visibility Page Address Pointer Register
RCOUNT 0036 Repeat Loop Counter Register
SR 0042 — — — — — — — DC IPL2 IPL1 IPL0 RA N
CORCON 0044 — — — — — — — — — — — —
IPL3
DISICNT 0052 —
— Disable Interrupts Counter
Register
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

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