# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 -- Serial Peripheral Interface

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 2014 Microchip Technology Inc. DS70005185A-page 29
Serial Peripheral Interface (SPI) Module
3.5.3 SPI MASTER/FRAMED SLAVE MODE
In SPI Master/Framed Slave mode, the module generates the clock signal, but uses the Slave
module’s frame synchronization signal for data transmission (see Figure 3-10). It is enabled by
setting the MSTEN, FRMEN and SPIFSD bits (SPIxCON1<5> and SPIxCON2<15:14>) to ‘1’.
In this mode, the SSx
pin is an input. It is sampled on the sample edge of the SPIx clock. When
it is sampled in its active state, data is transmitted on the subsequent transmit edge of the SPIx
clock. The SPIx Interrupt Flag, SPIxIF, is set when the transmission is complete. The user
application must make sure that the correct data is loaded into the SPIxBUF register for
transmission before the signal is received at the SSx
pin.
Figure 3-10: SPIx Master/Framed Slave Connection Diagram
Figure 3-11: SPIx Master/Framed Slave Timing (FRMDLY = 0)
SDOx
SDIx
dsPIC33/PIC24
Serial Clock
SSx
SCKx
Frame Sync
Pulse
SDIx
SDOx
PROCESSOR 2
SSx
SCKx
(SPIx Master/Framed Slave)
SCKx
(CKP = 0)
bit 14 bit 13 bit 12
SDIx
Sample SSx
pin for Pulse
Receive Samples at SDIx
bit 14 bit 13 bit 12
Write to SPIxBUF
SCKx
(CKP = 1)
SSx
(FRMPOL = 1)
SSx
(FRMPOL = 0)
bit 15
bit 15
SDOx

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