# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 244 © 2005-2011 Microchip Technology Inc.
FBCL
Find First Bit Change from Left
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} FBCL Ws, Wnd
[Ws],
[Ws++],
[Ws--],
[++Ws],
[--Ws],
Operands: Ws ∈ [W0 ... W15]
Wnd ∈ [W0 ... W15]
Operation: Max_Shift = 15
Sign = (Ws) & 0x8000
Temp = (Ws) << 1
Shift = 0
While ( (Shift < Max_Shift) && ( (Temp & 0x8000) == Sign) )
Temp = Temp << 1
Shift = Shift + 1
-Shift → (Wnd)
Status Affected: C
Encoding:
1101 1111 0000 0ddd dppp ssss
Description: Find the first occurrence of a one (for a positive value), or zero (for a
negative value), starting from the Most Significant bit after the sign bit of
Ws and working towards the Least Significant bit of the word operand. The
bit number result is sign-extended to 16 bits and placed in Wnd.
The next Most Significant bit after the sign bit is allocated bit number 0 and
the Least Significant bit is allocated bit number -14. This bit ordering
allows for the immediate use of Wd with the SFTAC instruction for scaling
values up. If a bit change is not found, a result of -15 is returned and the C
flag is set. When a bit change is found, the C flag is cleared.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note: This instruction operates in Word mode only.
Words: 1
Cycles:
1
(1)
Note 1:
In dsPIC33E and PIC24E devices, the listed cycle count does not apply to read and
read-modify-write operations on non-CPU Special Function Registers. For more
details, see
Note 3
in
Section 3.2.1 “Multi-Cycle Instructions”
.

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