# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- UART

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dsPIC33/PIC24 Family Reference Manual
DS70000582E-page 14  2009-2013 Microchip Technology Inc.
4.0 UART CONFIGURATION
The UART uses the standard Non-Return-to-Zero (NRZ) format (one Start bit, eight or nine Data
bits and one or two Stop bits). Parity is supported by the hardware and can be configured by the
user application as even, odd or no parity. The most common data format is eight bits, no parity
and one Stop bit (denoted as 8, N, 1), which is the default (POR) setting. The number of data
bits, Stop bits and the parity are specified in the PDSEL<1:0> (UxMODE<2:1>) and STSEL
(UxMODE<0>) bits. An on-chip, dedicated, 16-bit Baud Rate Generator can be used to derive
standard baud rate frequencies from the oscillator. The UART transmits and receives the Least
Significant bit (LSb) first. The transmitter and receiver of the UART module are functionally
independent, but use the same data format and baud rate.
4.1 Enabling the UART
The UART module is enabled by setting the UARTEN (UxMODE<15>) and UTXEN
(UxSTA<10>) bits. Once enabled, the UxTX pin is configured as an output and the UxRX pin as
an input, overriding the TRISx and PORTx register bit settings for the corresponding I/O port
pins. The UxTX pin is at logic 1 when no transmission is taking place.
4.2 Disabling the UART
The UART module is disabled by clearing the UARTEN bit (UxMODE<15>). This is the default
state after any Reset. If the UART is disabled, all UART pins operate as port pins under the
control of their corresponding PORTx and TRISx bits.
Disabling the UART module resets the buffers to empty states. Any data characters in the buffers
are lost and the baud rate counter is reset.
All error and status flags associated with the UART module are reset when the module is
disabled. The UTXBRK, UTXEN, UTXBF, PERR, FERR, OERR and URXDA bits are cleared,
whereas the TRMT and RIDLE bits are set. Other control bits (including ADDEN, URXISEL<1:0>
and UTXISEL<1:0>), and the UxMODE and UxBRG registers are not affected.
The clearing of the UARTEN bit while the UART is active will abort all pending transmissions and
receptions, and resets the module as defined above. Re-enabling the UART will restart the UART
in the same configuration.
Note: The UTXEN bit is set after the UARTEN bit has been set; otherwise, UART
transmissions will not be enabled.

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