# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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© 2005-2011 Microchip Technology Inc. DS70157F-page 31
Section 2. Programmer’s Model
Programmer’s
Model
2
Register 2-4: CORCON: Core Control Register (PIC24F and PIC24H Devices)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R/C-0 R/W-0 U-0 U-0
— — — — IPL3
(1,2)
PSV — —
bit 7 bit 0
Legend: C = Clearable bit R = Readable bit W = Writable bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
U = Unimplemented bit, read as ‘0’
bit 15-4 Unimplemented: Read as ‘0’
bit 3 IPL3: Interrupt Priority Level 3 Status bit
(1,2)
1 = CPU Interrupt Priority Level is 8 or greater (trap exception activated)
0 = CPU Interrupt Priority Level is 7 or less (no trap exception activated)
bit 2 PSV: Program Space Visibility in Data Space Enable bit
1 = Program space visible in data space
0 = Program space not visible in data space
bit 1-0 Unimplemented: Read as ‘0’
Note 1: This bit may be read or cleared, but not set.
2: This bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.

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