# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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 2007-2014 Microchip Technology Inc. DS70000195F-page 35
Inter-Integrated Circuit™ (I
2
C™)
6.3 Bus Arbitration and Bus Collision
The bus arbitration supports the multi-master system operation. The wired-AND nature of the
SDAx line permits arbitration. Arbitration takes place when the first master outputs ‘1’ on SDAx
by letting the SDAx float high, and simultaneously, the second master outputs ‘0’ on SDAx by
pulling SDAx low. The SDAx signal will go low. In this case, the second master has won bus
arbitration. The first master has lost bus arbitration, and thus, has a bus collision.
For the first master, the expected data on SDAx is ‘1’, still the data sampled on SDAx is ‘0’. This
is the definition of a bus collision.
The first master will set the BCL bit (I2CxSTAT<10>) and generates a master (MI2CxIF) or a bus
collision (I2CxBCIF) interrupt. The Master module will reset the I
2
C port to its Idle state.
In multi-master operation, the SDAx line must be monitored for arbitration to see if the signal level
is the expected output level. This check is performed by the master logic, with the result placed
in the BCL status bit.
The states where arbitration can be lost are:
• Start condition
• Repeated Start condition
• Address, Data or Acknowledge bit
• Stop condition
6.4 Detecting Bus Collisions and Re-Sending Messages
When a bus collision occurs, the master module sets the BCL status bit and generates a master
(MI2CxIF) or a bus collision (I2CxBCIF) interrupt. If a bus collision occurs during a byte
transmission, the transmission is stopped, the TBF status bit is cleared, and the SDAx and SCLx
pins are deasserted. If a bus collision occurs during a Start, Repeated Start, Stop or Acknowledge
condition, the condition is aborted, the respective control bits in the I2CxCON register are
cleared, and the SDAx and SCLx lines are deasserted.
The user software is expecting an interrupt at the completion of the master event. The user
software can check the BCL status bit to determine if the master event completed successfully
or a bus collision occurred (or it may branch to a bus collision interrupt on bus collision), or a
master interrupt occurred in case of a successful master event. If a bus collision occurs, the user
software must abort sending the rest of the pending message and prepare to re-send the entire
message sequence, beginning with the Start condition, after the bus returns to the Idle state. The
user software can monitor the S and P status bits to wait for an Idle bus. When the user software
executes the master Interrupt Service Routine (ISR) and the I
2
C bus is free, the user software
can resume communication by asserting a Start condition.
6.5 Bus Collision During a Start Condition
Before issuing a Start condition, the user software should verify an Idle state of the bus using the
S and P status bits. Two masters may attempt to initiate a message at a similar point in time.
Typically, the masters will synchronize clocks and continue arbitration into the message until one
loses arbitration. Any of the following conditions can cause a bus collision to occur during a Start:
• If the SDAx and SCLx pins are at a low logic state at the beginning of the Start condition
• If the SCLx line is at a low logic state before the SDAx line is driven low
In either case, the master that loses arbitration during the Start condition generates a bus
collision interrupt.
Note: The bus collision interrupt is not available on all devices. Refer to the specific device
data sheet for availability.
Note: The bus collision interrupt is not available on all devices. Refer to the specific device
data sheet for availability.

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