# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004

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 2010-2013 Microchip Technology Inc. DS39881E-page 13
PIC24FJ64GA004 FAMILY
OSCI 9 6 30 I ANA Main Oscillator Input Connection.
OSCO 10 7 31 O ANA Main Oscillator Output Connection.
PGEC1 5 2 22 I/O ST In-Circuit Debugger/Emulator and ICSP Programming
Clock.
PGEC2 22 19 9 I/O ST
PGEC3 14 12 42 I/O ST
PGED1 4 1 21 I/O ST In-Circuit Debugger/Emulator and ICSP Programming
Data.
PGED2 21 18 8 I/O ST
PGED3 15 11 41 I/O ST
PMA0 10 7 3 I/O ST/TTL Parallel Master Port Address Bit 0 Input (Buffered Slave
modes) and Output (Master modes).
PMA1 12 9 2 I/O ST/TTL Parallel Master Port Address Bit 1 Input (Buffered Slave
modes) and Output (Master modes).
PMA2   27 O  Parallel Master Port Address (Demultiplexed Master
modes).
PMA3   38 O 
PMA4   37 O 
PMA5   4 O 
PMA6   5 O 
PMA7   13 O 
PMA8   32 O 
PMA9   35 O 
PMA10   12 O 
PMA11    O 
PMA12    O 
PMA13    O 
PMBE 11 8 36 O  Parallel Master Port Byte Enable Strobe.
PMCS1 26 23 15 O  Parallel Master Port Chip Select 1 Strobe/Address Bit 14.
PMD0 23 20 10 I/O ST/TTL Parallel Master Port Data (Demultiplexed Master mode) or
Address/Data (Multiplexed Master modes).
PMD1 22 19 9 I/O ST/TTL
PMD2 21 18 8 I/O ST/TTL
PMD3 18 15 1 I/O ST/TTL
PMD4 17 14 44 I/O ST/TTL
PMD5 16 13 43 I/O ST/TTL
PMD6 15 12 42 I/O ST/TTL
PMD7 14 11 41 I/O ST/TTL
PMRD 24 21 11 O  Parallel Master Port Read Strobe.
PMWR 25 22 14 O  Parallel Master Port Write Strobe.
TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Function
Pin Number
I/O
Input
Buffer
Description
28-Pin
SPDIP/
SSOP/SOIC
28-Pin
QFN
44-Pin
QFN/TQFP
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I
2
C = I
2
C/SMBus input buffer
Note 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared.

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