# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 -- Errata

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 2009-2013 Microchip Technology Inc. DS80000470H-page 15
PIC24FJ64GA004 FAMILY
37. Module: I
2
C (Slave Mode)
Under certain circumstances, a module operating in
Slave mode may not respond correctly to some of
the special addresses reserved by the I
2
C protocol.
This happens when the following occurs:
• 10-Bit Addressing mode is used (A10M = 1);
and
• bits, A<7:1>, of the slave address
(I2CADD<7:1>) fall into the range of the
reserved 7-bit address ranges: ‘1111xxx’ or
‘0000xxx’.
In these cases, the Slave module Acknowledges
the command and triggers an I
2
C slave interrupt; it
does not copy the data into the I2CxRCV register
or set the RBF bit.
Work around
Do not set bits, A<7:1>, of the module’s slave
address equal to ‘1111xxx’ or ‘0000xxx’.
Affected Silicon Revisions
38. Module: I
2
C
The Transmit Buffer Full flag, TBF (I2CxSTAT<0>),
may not be cleared by hardware if a collision on
the I
2
C bus occurs before the first falling clock
edge during a transmission.
Work around
None.
Affected Silicon Revisions
39. Module: UART
When the UARTx is operating using two Stop bits
(STSEL = 1), it may sample the first Stop bit
instead of the second one. If the device being
communicated with is one using one Stop bit in its
communications, this may lead to framing errors.
Work around
None.
Affected Silicon Revisions
40. Module: Oscillator (SOSC)
The low-power Secondary Oscillator (SOSC)
option, selected by the SOSCSEL Configuration
bits (CW2<12:11>), is not available in this silicon
revision. The oscillator in all devices functions in the
Default (High-Gain) mode only.
Work around
None.
Affected Silicon Revisions
41. Module: Voltage Regulator
The Standby mode wake-up option, selected by
the WUTSEL Configuration bits (CW2<14:13>), is
not available in this silicon revision. All devices use
the default regulator wake-up time of 190 s.
Work around
None.
Affected Silicon Revisions
A3/
A4
B4 B5
B8
X X X
X
A3/
A4
B4 B5
B8
X
A3/
A4
B4 B5
B8
X X X
X
A3/
A4
B4 B5 B8
X
A3/
A4
B4 B5
B8
X

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