# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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dsPIC33/PIC24 Family Reference Manual
DS70000195F-page 20  2007-2014 Microchip Technology Inc.
5.0 COMMUNICATING AS A MASTER IN A SINGLE MASTER ENVIRONMENT
The I
2
C module’s typical operation in a system is using the I
2
C to communicate with an I
2
C
peripheral, such as an I
2
C serial memory. In an I
2
C system, the master controls the sequence of
all data communication on the bus. In this example, the dsPIC33/PIC24 device and its I
2
C
module have the role of the single master in the system. As the single master, it is responsible
for generating the SCLx clock and controlling the message protocol.
The I
2
C module controls individual portions of the I
2
C message protocol; however, sequencing
of the components of the protocol to construct a complete message is performed by the user
software.
For example, a typical operation in a single master environment is to read a byte from an I
2
C
serial EEPROM. Figure 5-1 illustrates the example message.
To accomplish this message, the user software will sequence through the following steps:
1. Assert a Start condition on SDAx and SCLx.
2. Send the I
2
C device address byte to the slave with a write indication.
3. Wait for and verify an Acknowledge from the slave.
4. Send the serial memory address high byte to the slave.
5. Wait for and verify an Acknowledge from the slave.
6. Send the serial memory address low byte to the slave.
7. Wait for and verify an Acknowledge from the slave.
8. Assert a Repeated Start condition on SDAx and SCLx.
9. Send the device address byte to the slave with a read indication.
10. Wait for and verify an Acknowledge from the slave.
11. Enable the master reception to receive serial memory data.
12. Generate an ACK
or NACK condition at the end of a received byte of data.
13. Generate a Stop condition on SDAx and SCLx.
Figure 5-1: A Typical I
2
C™ Message: Read of Serial EEPROM (Random Address Mode)
The I
2
C module supports Master mode communication with the inclusion of the Start and Stop
generators, data byte transmission, data byte reception, Acknowledge generator and a BRG.
Generally, the user software will write to a control register to start a particular step, then wait for
an interrupt or poll status to wait for completion. These operations are discussed in the
subsequent sections.
Note: The IPMIEN bit (I2CxCON<11>) should not be set when operating as a master.
Bus
Master
SDAx
Start
Address
Byte
EEPROM Address
High Byte
EEPROM Address
Low Byte
Address
Byte
Data
Byte
S 1 0 1 0
A A A
0
2 1 0
R 1 0 1 0
A A A
1
2 1 0
P
Slave
SDAx
Activity
N
AAAA
Output
Output
Idle
R/W
ACK
ACK
ACK
Restart
R/W
ACK
NACK
Stop
Idle
Note: The I
2
C module does not allow queuing of events. For example, the user software
is not allowed to initiate a Start condition, and immediately write the I2CxTRN
register to initiate transmission, before the Start condition is complete. In this case,
the I2CxTRN register will not be written to and the IWCOL status bit (I2CxSTAT<7>)
will be set, indicating that this write to the I2CxTRN register did not occur.

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