# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 -- Serial Peripheral Interface

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dsPIC33/PIC24 Family Reference Manual
DS70005185A-page 14  2014 Microchip Technology Inc.
3.3.1 MASTER MODE
In Master mode, the system clock is prescaled and then used as the serial clock. The prescaling is
based on the settings in the Primary Prescale bits (PPRE<1:0>) and the Secondary Prescale bits
(SPRE<2:0>) in the SPIxCON1 register. The serial clock is output through the SCKx pin to slave
devices. The clock pulses are generated only when there is data to be transmitted (see Section 4.0
“Master Mode Clock Frequency”). The SPIx Clock Polarity Select bit, CKP (SPIxCON1<6>), and
the SPIx Clock Edge Select bit, CKE (SPIxCON1<8>), determine the edge of the clock pulse on
which data transmission occurs. Both data to be transmitted and data received are, respectively,
written into or read from the SPIxBUF register.
The SPIx module operation in Master mode is as described:
1. Once the module is set up in Master mode and enabled to operate, data to be transmitted
is written into the SPIxBUF register. The SPIx Transmit Buffer Full Status bit (SPITBF) in
the SPIx Status and Control register (SPIxSTAT<1>) is set.
2. The content of the SPIx Transmit Buffer register (SPIxTXB) is moved to the SPIxSR
register and the SPITBF bit (SPIxSTAT<1>) is cleared by the module.
3. A series of 8/16 clock pulses shift out 8/16 bits of transmit data from the SPIxSR register
to the SDOx pin, and simultaneously, shift the data at the SDIx pin into the SPIxSR
register.
4. When the transfer is complete, the following events occur in the interrupt controller:
a) The appropriate interrupt flag bit is set in the interrupt controller:
• The SPIxIF bit is set in the Interrupt Flag Status register x (IFSx)
• The SPIxIF flags are not cleared automatically by the hardware
b) When the ongoing transmit and receive operations are completed, the content of the
SPIxSR register is moved to the SPIx Receive Buffer (SPIxRXB) register.
c) The SPIx Receive Buffer Full Status bit, SPIRBF (SPIxSTAT<0>), is set by the
module, indicating that the receive buffer is full. Once the SPIxBUF register is read
by the user application, the hardware clears the SPIRBF bit.
5. If the SPIRBF bit (SPIxSTAT<0>) is set (receive buffer is full) when the SPIx module needs
to transfer data from the SPIxSR register to the SPIxRXB register, the module sets the
SPIx Receive Overflow Flag bit (SPIROV) in the SPIxSTAT register (SPIxSTAT<6>),
indicating an overflow condition.
6. Data to be transmitted can be written to the SPIxBUF register by the user application at
any time as long as the SPITBF bit (SPIxSTAT<1>) is clear. The write can occur while the
SPIxSR register is transferring the previously written data, allowing continuous
transmission.
Note 1: For devices with the PPS feature, when the SPIx module is configured as a Master,
the SCKx pin must be mapped as both input and output.
2: The user application cannot write directly into the SPIxSR register. All writes to the
SPIxSR register are performed through the SPIxBUF register.
3: In Master mode, the SPIx module does not control the SSx
pin. This pin should be
configured as a General Purpose I/O (GPIO) by clearing the SSEN bit
(SPIxCON1<7>) = 0.

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