# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Serial Peripheral Interface

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© 2007 Microchip Technology Inc. Advance Information DS39699B-page 23-4
Section 23. Serial Peripheral Interface (SPI)
Serial Peripheral
Interface (SPI)
23
23.2 STATUS AND CONTROL REGISTERS
The SPIx serial port consists of the following Special Function Registers:
• SPIxBUF: The address in SFR space that is used to buffer data to be transmitted and data
that is received (in Standard modes) or to access the FIFO buffer (in Enhanced Buffer
modes). This address is shared by the virtual SPIxTXB and SPIxRXB registers.
• SPIxCON1 and SPIxCON2: Control registers that configure the module for various modes
of operation.
• SPIxSTAT: A status register that indicates various status conditions.
In addition, a 16-bit shift register, SPIxSR, is used for shifting data in and out of the SPIx port.
The shift register is not memory mapped.
23.2.1 SPIxBUF Register
The memory mapped register, SPIxBUF, is the SPIx Data Receive/Transmit register. In Standard
modes, the SPIxBUF register is actually comprised of two separate registers: the Transmit Buffer,
SPIxTXB, and the Receive Buffer, SPIxRXB. These two unidirectional, 16-bit registers share the
SFR address of SPIxBUF. If a user writes data to be transmitted to the SPIxBUF address,
internally the data is written to the SPIxTXB register. Similarly, when the user reads the received
data from SPIxBUF, internally the data is read from the SPIxRXB register.
When the enhanced buffer is enabled, SPIxBUF becomes the data interface to two 8-level
FIFOs: one for reception and another for transmission. Each buffer can hold up to eight pending
data transfers. When the CPU writes data to SPIxBUF, the data is moved into the next transmit
buffer location. The SPIx peripheral begins to transfer data after the first CPU write to SPIxBUF,
and continues until all pending transfers have completed. After each transfer completes, the SPIx
updates the next receive buffer location with the received data and is available for the CPU to
read. After the CPU read, data is read from the next receive buffer location.
Both modes double-buffer transmit and receive operations and allow continuous data transfers
in the background. Transmission and reception occur simultaneously.
23.2.2 Status and Control Registers
The SPIxSTAT and SPIxCON1/SPIxCON2 registers provide the interface to control the module’s
operation. They are shown in detail in Register 23-1, Register 23-2 and Register 23-3.
Note: In Standard modes, the SPIxBUF register must not be written before SPIxTBF bit is
set. Similarly, the SPIxBUF register must not be read before the SPIxRBF bit is set.
Note: SPIxCON1 and SPIxCON2 can not be written while the SPIx modules are enabled.
The SPIEN (SPIxSTAT<15>) bit must be clear before modifying either register.

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