# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Serial Peripheral Interface

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PIC24F Family Reference Manual
DS39699B-page 23-23 Advance Information © 2007 Microchip Technology Inc.
23.3.5 SPIx Receive Only Operation
Setting the DISSDO control bit (SPIxCON1<11>) disables transmission at the SDOx pin. This
allows the SPIx module to be configured for a Receive Only mode of operation. The SDOx pin
will be controlled by the respective port function if the DISSDO bit is set.
The DISSDO function is applicable to all SPIx operating modes.
23.3.6 SPIx Error Handling
If a new data word has been shifted from the SPIx bus into SPIxSR, and no more unread buffer
locations are available, the SPIROV bit (SPIxSTAT<6>) will be set. Any received data in SPIxSR
will not be transferred and further data reception is disabled until the SPIROV bit is cleared. The
SPIROV bit is not cleared automatically by the module; it must be cleared by the user software.
The SPIx Interrupt Flag, SPFxIF, is set whenever the SPIROV, SPIxRBF (SPIxSTAT<0>) or
SPIxTBF (SPIxSTAT<1>) bits are set. The interrupt flag cannot be cleared by hardware and must
be reset in software. The actual SPIx interrupt is generated only when the corresponding SPFxIE
bit is set in the IECn Control register
23.4 SPI MASTER MODE CLOCK FREQUENCY
In the Master mode, the clock provided to the SPIx module is the instruction cycle (T CY). This
clock will then be prescaled by the primary prescaler, specified by the PPRE1:PPRE0 bits
(SPIxCON1<1:0>) and the secondary prescaler, specified by the SPRE2:SPRE0 bits
(SPIxCON1<4:2>). The prescaled instruction clock becomes the serial clock and is provided to
external devices via the SCKx pin.
Equation 23-1 can be used to calculate the SCKx clock frequency as a function of the primary
and secondary prescaler settings.
Equation 23-1:
Some sample SPIx clock frequencies (in kHz) are shown in Table 23-2:
Table 23-1: Sample SCK Frequencies
(1,2)
Note: Note that the SCKx signal clock is not free running for normal SPI modes. It will only
run for 8 or 16 pulses when the SPIxBUF is loaded with data. It will, however, be
continuous for Framed modes.
FCY = 16 MHz
Secondary Prescaler Settings
1:1 2:1 4:1 6:1 8:1
Primary Prescaler Settings 1:1 (Invalid) 8000 4000 2667 2000
4:1 4000 2000 1000 667 500
16:1 1000 500 250 167 125
64:1 250 125 63 42 31
F
CY = 5 MHz
Primary Prescaler Settings 1:1 5000 2500 1250 833 625
4:1 1250 625 313 208 156
16:1 313 156 78 52 39
64:1 78 39 20 13 10
Note 1: Based on T
CY = T OSC/2; Doze mode and PLL are disabled.
2: SCKx frequencies shown in kHz.
Primary Prescaler * Secondary Prescaler
F
CY
F
SCK =
Note: Not all clock rates are supported. For further information, refer to the SPIx timing
specifications in the specific device data sheet.

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