# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 220 © 2005-2011 Microchip Technology Inc.
DEC2
Decrement f by 2
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} DEC2{.B} f {,WREG}
Operands: f ∈ [0 ... 8191]
Operation: (f) – 2 → destination designated by D
Status Affected: DC, N, OV, Z, C
Encoding: 1110 1101 1BDf ffff ffff ffff
Description: Subtract two from the contents of the file register and place the result in the
destination register. The optional WREG operand determines the
destination register. If WREG is specified, the result is stored in WREG. If
WREG is not specified, the result is stored in the file register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
Words: 1
Cycles:
1
(1)
Note 1:
In dsPIC33E and PIC24E devices, the listed cycle count does not apply to read and
read-modify-write operations on non-CPU Special Function Registers. For more
details, see
Note 3
in
Section 3.2.1 “Multi-Cycle Instructions”
.
Example 1:
DEC2.B 0x200 ; Decrement (0x200) by 2 (Byte mode)
Before
Instruction
After
Instruction
Data 200 80FF Data 200 80FD
SR 0000 SR 0009 (N, C = 1)
Example 2:
DEC2 RAM400, WREG ; Decrement RAM400 by 2 and
; store to WREG (Word mode)
Before
Instruction
After
Instruction
WREG 1211 WREG 0821
RAM400 0823 RAM400 0823
SR 0000 SR 0000

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