# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- CPU

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PIC24F Family Reference Manual
DS39703A-page 2-22 Advance Information © 2006 Microchip Technology Inc.
2.11 ADDRESS REGISTER DEPENDENCIES
The PIC24F architecture supports a data space read (source) and a data space write
(destination) for most instructions. The Effective Address (EA) calculation by the Address Gener-
ator Unit (AGU), and subsequent data space read or write, each take a period of one instruction
cycle to complete. This timing causes the data space read and write operations for each instruc-
tion to partially overlap, as shown in Figure 2-9. Because of this overlap, a ‘Read-After-Write’
(RAW) data dependency can occur across instruction boundaries. RAW data dependencies are
detected and handled at run time by the PIC24F CPU.
Figure 2-9: Data Space Access Timing
2.11.1 Read-After-Write Dependency Rules
If a working register, Wn, is used as a write operation destination in the current instruction, and the
same working register, Wn, being read in the prefetched instruction are the same, the following
rules will apply:
1. If the destination write (current instruction) does not modify the contents of Wn, no stalls
will occur;
or
2. If the source read (prefetched instruction) does not calculate an EA using Wn, no stalls
will occur.
During each instruction cycle, the PIC24F hardware automatically checks to see if a RAW data
dependency is about to occur. If the conditions specified above are not satisfied, the CPU will
automatically add a one instruction cycle delay before executing the prefetched instruction. The
instruction stall provides enough time for the destination W register write to take place before the
next (prefetched) instruction has to use the written data.
ADD MOV
[W7]
[W10] [W9]++
Address
W7 W10 W8 W9
ADD W0, [W7], [W10]
MOV [W8], [W9]++
[W8]
Read AGU
Instruction Register
Contents
Write AGU
1 Instruction Cycle (T CY)
T
CY0 T CY1 T CY2

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