# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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 2007-2014 Microchip Technology Inc. DS70000195F-page 11
Inter-Integrated Circuit™ (I
2
C™)
Register 3-2: I2CxCONL: I2Cx Control Register Low
R/W-0 U-0 R/W-0, HC R/W-1 R/W-0 R/W-0 R/W-0 R/W-0
I2CEN
— I2CSIDL SCLREL
(1)
STRICT A10M DISSLW SMEN
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC
GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0
Legend: HC = Hardware Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 I2CEN: I2Cx Enable bit
1 = Enables the I
2
C™ module and configures the SDAx and SCLx pins as serial port pins
0 = Disables the I
2
C module; all the I
2
C pins are controlled by port functions
bit 14 Unimplemented: Read as ‘0’
bit 13 I2CSIDL: I2Cx Stop in Idle Mode bit
1 = Discontinues the module operation when a device enters Idle mode
0 = Continues the module operation in the Idle mode
bit 12 SCLREL: SCLx Release Control bit (I
2
C Slave mode only)
(1)
Module resets and (I2CEN = 0) sets SCLREL = 1.
If STREN =
0:
(2)
1 = Releases the clock
0 = Forces clock low (clock stretch)
If STREN =
1:
1 = Releases the clock
0 = Holds clock low (clock stretch); the user may program this bit to ‘0’, clock stretch at next SCLx low
bit 11 STRICT: Strict I
2
C Reserved Address Rule Enable bit
1 = Strict reserved addressing is enforced; for reserved addresses
In a Slave mode, the device does not respond to reserved address space and the addresses falling
in that category are NACKed.
In a Master mode, the device is allowed to generate addresses with the reserved address space.
0 = Reserved addressing would be Acknowledged
In a Slave mode, the device will respond to an address falling in the reserved address space. When
there is a match with any of the reserved addresses, the device will generate an ACK
.
In a Master mode, it is reserved.
bit 10 A10M: 10-Bit Slave Address Flag bit
1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address
bit 9 DISSLW: Slew Rate Control Disable bit
1 = Slew rate control is disabled for Standard Speed mode (100 kHz, disabled for 1 MHz mode)
0 = Slew rate control is enabled for High-Speed mode (400 kHz)
bit 8 SMEN: SMBus Input Levels Enable bit
1 = Enables the input logic; therefore, thresholds are compliant with the SMBus specification
0 = Disables the SMBus-specific inputs
Note 1: Automatically cleared to ‘0’ at the beginning of the slave transmission; automatically cleared to ‘0’ at the
end of the slave reception.
2: Automatically cleared to ‘0’ at the beginning of the slave transmission.

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