# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 -- UART

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 2009-2013 Microchip Technology Inc. DS70000582E-page 21
UART
7.0 UART RECEIVER
The receiver block diagram of the UART module is illustrated in Figure 7-1. The important part
of the receiver is the UARTx Receive (Serial) Shift Register (UxRSR). The data is received on
the UxRX pin and is sent to the data recovery block. After sampling the UxRX pin for the Stop bit,
the received data in the UxRSR register is transferred to the receive FIFO (if it is empty). The
data recovery block operates at 16 times the baud rate, whereas the main receive serial shifter
operates at the baud rate.
The data on the UxRX pin is sampled multiple times by a Majority Detect circuit to determine if a
high or a low level is present at the UxRX pin.
7.1 Receive Buffer (UxRXREG)
The UART receiver has a 4 deep, 9-bit wide FIFO receive data buffer. The UxRXREG is a
memory mapped register that provides access to the output of the FIFO. It is possible for four
words of data to be received and transferred to the FIFO, and a fifth word to begin shifting to the
UxRSR register before a buffer overrun occurs.
7.2 Receiver Error Handling
If the FIFO is full (four characters) and a fifth character is fully received into the UxRSR register,
the OERR bit (UxSTA<1>) will be set. The word in the UxRSR register will be kept, but further
transfers to the receive FIFO and UART interrupts are inhibited as long as the OERR bit is set.
The user application must clear the OERR bit in software to allow further data to be received.
If it is desired to keep the data received prior to the overrun, the user application should first read
all five characters, then clear the OERR bit. If the five characters can be discarded, the user
application can simply clear the OERR bit. This effectively resets the receive FIFO and all prior
received data is lost.
The Framing Error bit, FERR (UxSTA<2>), is set if a Stop bit is detected at a logic low level.
The Parity Error bit, PERR (UxSTA<3>), is set if a parity error has been detected in the data word
at the top of the buffer (i.e., the current word). For example, a parity error would occur if the parity
is set to be even, but the total number of 1s in the data has been detected to be odd. The PERR
bit is irrelevant in 9-bit mode. The FERR and PERR bits are buffered along with the
corresponding word and should be read before reading the data word.
An interrupt is generated if any of these (OERR, FERR and PERR) errors occur. The user
application needs to enable the corresponding UARTx Interrupt Enable Control bit (UxERIE) in
the IECx register to go to the corresponding interrupt vector location.
Note: The UxRSR register is not mapped in the data memory, so it is not available to the
user application.
Note: The data in the receive FIFO should be read prior to clearing the OERR bit. The
FIFO is reset when OERR is cleared, which causes all data in the buffer to be lost.
Note: After a Reset, the three possible UART interrupts have the same Interrupt Priority
Level (IPL). Natural order allows the (RX/TX) data interrupts to be serviced before
the UART error interrupt.
To allow the UART error interrupt to be serviced before the (RX/TX) data interrupts,
its Interrupt Priority Level (UxEIP) is raised or the data Interrupt Priority Levels are
lowered (UxRXIP and UxTXIP).
Example for UART2 to raise the UART2 error interrupt level:
 IPC7bits.U2RXIP = 4; //UART2 RX interrupt priority, mid-range
 IPC7bits.U2TXIP = 4; //UART2 TX interrupt priority, mid-range
 IPC16bits.U2EIP = 5; //UART2 error priority set higher

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