# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Family Data Sheet

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© 2011-2012 Microchip Technology Inc. Preliminary DS39997C-page 53
TABLE 4-31: SYSTEM CONTROL REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit
RCON 0740 TRAPR IOPUWR — — — — CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE
OSCCON 0742 — COSC<2:0> — NOSC<2:0> CLKLOCK IOLOCK LOCK — CF —
CLKDIV 0744 ROI DOZE<2:0> DOZEN FRCDIV<2:0> — — — — — —
OSCTUN 0748
— — — — — — — — — — TUN<5:0>
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: RCON register Reset values dependent on type of Reset.
2: OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset.
TABLE 4-32: NVM REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
NVMCON 0760 WR WREN WRERR — — — — — — ERASE — — N
NVMKEY 0766
— — — — — — — — NVMKEY<7:0>
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
TABLE 4-33: PMD REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B
PMD1 0770 T5MD
(1)
T4MD
(1)
T3MD T2MD T1MD
—
PWM1MD
—
I2C1MD
—
U1MD
—
SPI1MD
PMD2 0772
— — — — — IC3MD IC2MD IC1MD — — — — —
PMD3 0774
— — — — — CMPMD RTCCMD — — — — — —
PMD4 0776
— — — — — — — — — — — — — CT
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This bit is available in PIC24FJ32MC101/102/104 devices only.

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