# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Family Data Sheet

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© 2011-2012 Microchip Technology Inc. Preliminary DS39997C-page 175
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)
(3)
111 = Secondary prescale 1:1
110 = Secondary prescale 2:1
•
•
•
000 = Secondary prescale 8:1
bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)
(3)
11 = Primary prescale 1:1
10 = Primary prescale 4:1
01 = Primary prescale 16:1
00 = Primary prescale 64:1
REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED)
Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes
(FRMEN = 1).
2: This bit must be cleared when FRMEN = 1.
3: Do not set both Primary and Secondary prescalers to a value of 1:1.

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