# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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dsPIC33/PIC24 Family Reference Manual
DS70000195F-page 44  2007-2014 Microchip Technology Inc.
7.3.5 10-BIT ADDRESSING MODE
In 10-Bit Addressing mode, the slave must receive two device address bytes, as illustrated in
Figure 7-7. The 5 Most Significant bits (MSbs) of the first address byte specify a 10-bit address.
The R/W
status bit of the address must specify a write, causing the slave device to receive the
second address byte. For a 10-bit address, the first byte would equal, ‘11110 A9 A8 0’, where
A9 and A8 are the 2 MSbs of the address.
The I2CxMSK register can mask any bit position in a 10-bit address. The 2 MSbs of the I2CxMSK
register are used to mask the MSbs of the incoming address received in the first byte. The remaining
byte of the register is then used to mask the lower byte of the address received in the second byte.
Following the Start condition, the module shifts eight bits into the I2CxRSR register. The value of
the I2CxRSR<2:1> bits is evaluated against the value of the I2CxADD<9:8> and I2CxMSK<9:8>
bits, while the value of the I2CxRSR<7:3> bits is compared to ‘11110’. Address evaluation
occurs on the falling edge of the eighth SCLx clock. For the address to be valid, the
I2CxRSR<7:3> bits must be equal to ‘11110’, while the I2CxRSR<2:1> bits must exactly match
any unmasked bits in the I2CxADD<9:8> bits (if both bits are masked, a match is not needed). If
the address is valid, the following events occur:
• An ACK
is generated
• The D/A
and R/W status bits are cleared
• The module generates the SI2CxIF interrupt on the falling edge of the ninth SCLx clock
The module does generate an interrupt after the reception of the first byte of a 10-bit address;
however, this interrupt is of little use.
The module will continue to receive the second byte into the I2CxRSR register. This time, the
I2CxRSR<7:0> bits are evaluated against the I2CxADD<7:0> and I2CxMSK<7:0> bits. If the
lower byte of the address is valid, as previously described, the following events occur:
• An ACK
is generated
• The ADD10 status bit is set
• The module generates the SI2CxIF interrupt on the falling edge of the ninth SCLx clock
• The module will wait for the master to send data or initiate a Repeated Start condition
Figure 7-7: 10-Bit Address Detection Timing Diagram (AHEN = 0)
Note: Following a Repeated Start condition in 10-Bit Addressing mode, the slave only
matches the first 7-bit address, ‘11110 A9 A8 0’.
SCLx (Master)
SDAx (Master)
SDAx (Slave)
SI2CxIF Interrupt
2
4 51 3
Detecting the Start bit enables address detection.
1
Address match of first byte clears the D/A
status bit and causes slave logic to generate an ACK.
2
Reception of first byte clears the R/W
status bit. Slave logic generates an interrupt.
3
Address match of first and second byte sets the ADD10 status bit and causes slave logic to generate an ACK
.
4
Reception of second byte completes the 10-bit address. Slave logic generates an interrupt.
5
I
2
C™ Bus State
(D) (D) (A)(D)
111 1 0
A9 A8
R/W
= 0
D/A
ADD10
SCLREL
A5A6A7 A4 A3 A2 A1 A0
R/W
(D) (D) (A)(D)
6
(S) (Q)

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