# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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© 2005-2011 Microchip Technology Inc. DS70157F-page 95
Section 5. Instruction Descriptions
Instruction
Descriptions
5
Table 5-2: Addressing Modes for Ws Source Register
Table 5-3: Addressing Modes for Wd Destination Register
Table 5-4: Offset Addressing Modes for Ws Source Register (with Register Offset)
Table 5-5: Offset Addressing Modes for Wd Destination Register
(with Register Offset)
ppp Addressing Mode Source Operand
000 Register Direct Ws
001 Indirect [Ws]
010 Indirect with Post-Decrement [Ws--]
011 Indirect with Post-Increment [Ws++]
100 Indirect with Pre-Decrement [--Ws]
101 Indirect with Pre-Increment [++Ws]
11x Unused
qqq Addressing Mode Destination Operand
000 Register Direct Wd
001 Indirect [Wd]
010 Indirect with Post-Decrement [Wd--]
011 Indirect with Post-Increment [Wd++]
100 Indirect with Pre-Decrement [--Wd]
101 Indirect with Pre-Increment [++Wd]
11x Unused (an attempt to use this Addressing mode will force a RESET instruction)
ggg Addressing Mode Source Operand
000 Register Direct Ws
001 Indirect [Ws]
010 Indirect with Post-Decrement [Ws--]
011 Indirect with Post-Increment [Ws++]
100 Indirect with Pre-Decrement [--Ws]
101 Indirect with Pre-Increment [++Ws]
11x Indirect with Register Offset [Ws+Wb]
hhh Addressing Mode Source Operand
000 Register Direct Wd
001 Indirect [Wd]
010 Indirect with Post-Decrement [Wd--]
011 Indirect with Post-Increment [Wd++]
100 Indirect with Pre-Decrement [--Wd]
101 Indirect with Pre-Increment [++Wd]
11x Indirect with Register Offset [Wd+Wb]

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