# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004

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PIC24FJ64GA004 FAMILY
DS39881E-page 216  2010-2013 Microchip Technology Inc.
24.2.3 ON-CHIP REGULATOR AND POR
When the voltage regulator is enabled, it takes approx-
imately 10 µs for it to generate output. During this time,
designated as T
VREG, code execution is disabled.
T
VREG is applied every time the device resumes oper-
ation after any power-down, including Sleep mode.
T
VREG is determined by the setting of the PMSLP bit
(RCON<8>) and the WUTSELx Configuration bits
(CW2<14:13>). For more information on T VREG, see
Section 27.0 “Electrical Characteristics”.
If the regulator is disabled, a separate Power-up Timer
(PWRT) is automatically enabled. The PWRT adds a
fixed delay of 64 ms nominal delay at device start-up
(POR or BOR only). When waking up from Sleep with
the regulator disabled, T
VREG is used to determine the
wake-up time. To decrease the device wake-up time
when operating with the regulator disabled, the PMSLP
bit can be set.
24.2.4 POWER-UP REQUIREMENTS
The on-chip regulator is designed to meet the power-up
requirements for the device. If the application does not
use the regulator, then strict power-up conditions must
be adhered to. While powering up, V
DDCORE must
never exceed V
DD by 0.3 volts.
24.2.5 VOLTAGE REGULATOR STANDBY
MODE
When enabled, the on-chip regulator always consumes
a small incremental amount of current over I
DD/IPD,
including when the device is in Sleep mode, even
though the core digital logic does not require power. To
provide additional savings in applications where power
resources are critical, the regulator automatically
places itself into Standby mode whenever the device
goes into Sleep mode. This feature is controlled by the
PMSLP bit (RCON<8>). By default, this bit is cleared,
which enables Standby mode.
For select PIC24FJ64GA004 family devices, the time
required for regulator wake-up from Standby mode is
controlled by the WUTSEL<1:0> Configuration bits
(CW2<14:13>). The default wake-up time for all
devices is 190 s. Where the WUTSELx Configuration
bits are implemented, a fast wake-up option is also
available. When WUTSEL<1:0> = 01, the regulator
wake-up time is 25 s.
When the regulators Standby mode is turned off
(PMSLP = 1), Flash program memory stays powered
in Sleep mode and the device can wake-up in less than
10 s. When PMSLP is set, the power consumption
while in Sleep mode will be approximately 40 A higher
than power consumption when the regulator is allowed
to enter Standby mode.
24.3 Watchdog Timer (WDT)
For PIC24FJ64GA004 family devices, the WDT is
driven by the LPRC oscillator. When the WDT is
enabled, the clock source is also enabled.
The nominal WDT clock source from LPRC is 31 kHz.
This feeds a prescaler that can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the FWPSA Configuration bit.
With a 31 kHz input, the prescaler yields a nominal
WDT Time-out period (T
WDT) of 1 ms in 5-bit mode or
4 ms in 7-bit mode.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPS<3:0> Con-
figuration bits (CW1<3:0>), which allow the selection of
a total of 16 settings, from 1:1 to 1:32,768. Using the
prescaler and postscaler, time-out periods, ranges from
1 ms to 131 seconds can be achieved.
The WDT, prescaler and postscaler are reset:
 On any device Reset
 On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
after changing the NOSCx bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
 When a PWRSAV instruction is executed
(i.e., Sleep or Idle mode is entered)
 When the device exits Sleep or Idle mode to
resume normal operation
 By a CLRWDT instruction during normal execution
If the WDT is enabled, it will continue to run during
Sleep or Idle modes. When the WDT time-out occurs,
the device will wake the device and code execution will
continue from where the PWRSAV instruction was
executed. The corresponding SLEEP or IDLE bits
(RCON<3:2>) will need to be cleared in software after
the device wakes up.
The WDT Flag bit, WDTO (RCON<4>), is not auto-
matically cleared following a WDT time-out. To detect
subsequent WDT events, the flag must be cleared in
software.
Note: For more information, see Section 27.0
“Electrical Characteristics”.
Note: This feature is implemented only on
PIC24FJ64GA004 family devices with a
major silicon revision level of B or later
(DEVREV register value is 3042h or
greater).
Note: The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.

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