# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004

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PIC24FJ64GA004 FAMILY
DS39881E-page 80  2010-2013 Microchip Technology Inc.
REGISTER 7-17: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
 U1RXIP2 U1RXIP1 U1RXIP0  SPI1IP2 SPI1IP1 SPI1IP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
 SPF1IP2 SPF1IP1 SPF1IP0  T3IP2 T3IP1 T3IP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as 0
bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)



001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11 Unimplemented: Read as 0
bit 10-8 SPI1IP<2:0>: SPI1 Event Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)



001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7 Unimplemented: Read as 0
bit 6-4 SPF1IP<2:0>: SPI1 Fault Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)



001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3 Unimplemented: Read as 0
bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)



001 = Interrupt is Priority 1
000 = Interrupt source is disabled

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