# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004

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PIC24FJ64GA004 FAMILY
DS39881E-page 190  2010-2013 Microchip Technology Inc.
FIGURE 20-2: CRC SHIFT ENGINE DETAIL
20.1 User Interface
20.1.1 DATA INTERFACE
To start serial shifting, a 1 must be written to the
CRCGO bit.
The module incorporates a FIFO that is 8 deep when
PLEN<3:0> (CRCCON<3:0>) > 7 and 16 deep, other-
wise. The data for which the CRC is to be calculated
must first be written into the FIFO. The smallest data
element that can be written into the FIFO is one byte.
For example, if PLEN<3:0> = 5, then the size of the
data is PLEN<3:0> + 1 = 6. When loading data, the
two MSbs of the data byte are ignored.
Once data is written into the CRCWDAT MSb (as
defined by PLENx), the value of VWORD<4:0>
(CRCCON<12:8>) increments by one. When
CRCGO = 1 and VWORDx > 0, a word of data to be
shifted is moved from the FIFO into the shift engine.
When the data word moves from the FIFO to the shift
engine, the VWORDx bits decrement by one. The serial
shifter continues to receive data from the FIFO, shifting
until the VWORDx bits reach 0. The last bit of data will
be shifted through the CRC module (PLENx + 1)/2 clock
cycles after the VWORDx bits reach 0. This is when the
module is completed with the CRC calculation.
Therefore, for a given value of PLENx, it will take
(PLENx + 1)/2 * VWORDx number of clock cycles to
complete the CRC calculations.
When the VWORD<4:0> bits reach 8 (or 16), the
CRCFUL bit will be set. When the VWORD<4:0> bits
reach 0, the CRCMPT bit will be set.
To continually feed data into the CRC engine, the
recommended mode of operation is to initially prime
the FIFO with a sufficient number of words, so no inter-
rupt is generated before the next word can be written.
Once that is done, start the CRC by setting the CRCGO
bit to 1. From that point onward, the VWORDx bits
should be polled. If they read less than 8 or 16, another
word can be written into the FIFO.
To empty words already written into a FIFO, the
CRCGO bit must be set to 1 and the CRC shifter
allowed to run until the CRCMPT bit is set.
Also, to get the correct CRC reading, it will be
necessary to wait for the CRCMPT bit to go high before
reading the CRCWDAT register.
If a word is written when the CRCFUL bit is set, the
VWORDx Pointer will roll over to 0. The hardware will
then behave as if the FIFO is empty. However, the con-
dition to generate an interrupt will not be met; therefore,
no interrupt will be generated (See Section 20.1.2
“Interrupt Operation”).
At least one instruction cycle must pass after a write to
CRCWDAT before a read of the VWORDx bits is done.
20.1.2 INTERRUPT OPERATION
When the VWORD<4:0> bits make a transition from a
value of 1 to 0, an interrupt will be generated. Note
that the CRC calculation is not complete at this point;
an additional time of (PLEN + 1)/2 clock cycles is
required before the output can be read.
20.2 Operation in Power Save Modes
20.2.1 SLEEP MODE
If Sleep mode is entered while the module is operating,
the module will be suspended in its current state until
clock execution resumes.
20.2.2 IDLE MODE
To continue full module operation in Idle mode, the
CSIDL bit must be cleared prior to entry into the mode.
If CSIDL = 1, the module will behave the same way as
it does in Sleep mode; pending interrupt events will be
passed on, even though the module clocks are not
available.
CRCWDAT
Bit n
(2)
X(1)
(1)
Read/Write Bus
Shift Buffer
Data
Bit 2
X(2)
(1)
X(n)
(1)
Note 1: Each XOR stage of the shift engine is programmable. See text for details.
2: Polynomial Length n is determined by ([PLEN<3:0>] + 1).
Bit 0
Bit 1

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