# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- CPU

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© 2006 Microchip Technology Inc. Advance Information DS39703A-page 2-23
Section 2. CPU
CPU
2
Table 2-4: Read-After-Write Dependency Summary
2.11.2 Instruction Stall Cycles
An instruction stall is essentially a one instruction cycle wait period appended in front of the read
phase of an instruction in order to allow the prior write to complete before the next read operation.
For the purposes of interrupt latency, it should be noted that the stall cycle is associated with the
instruction following the instruction where it was detected (i.e., stall cycles always precede
instruction execution cycles).
If a RAW data dependency is detected, the PIC24F will begin an instruction stall. During an
instruction stall, the following events occur:
1. The write operation underway (for the previous instruction) is allowed to complete as normal.
2. Data space is not addressed until after the instruction stall.
3. PC increment is inhibited until after the instruction stall.
4. Further instruction fetches are inhibited until after the instruction stall.
2.11.2.1 INSTRUCTION STALL CYCLES AND INTERRUPTS
When an interrupt event coincides with two adjacent instructions that will cause an instruction
stall, one of two possible outcomes could occur:
1. The interrupt could be coincident with the first instruction. In this situation, the first instruction
will be allowed to complete and the second instruction will be executed after the ISR
completes. In this case, the stall cycle is eliminated from the second instruction because the
exception process provides time for the first instruction to complete the write phase.
2. The interrupt could be coincident with the second instruction. In this situation, the second
instruction and the appended stall cycle will be allowed to execute prior to the ISR. In this
case, the stall cycle associated with the second instruction executes normally. However, the
stall cycle will be effectively absorbed into the exception process timing. The exception
process proceeds as if an ordinary 2-cycle instruction was interrupted.
Destination Addressing
Mode Using Wn
Source Addressing
Mode Using Wn
Status
Examples
(Wn = W2)
Direct Direct Allowed
ADD.w W0, W1, W2
MOV.w W2, W3
Direct Indirect Stall
ADD.w W0, W1, W2
MOV.w [W2], W3
Direct Indirect with
modification
Stall
ADD.w W0, W1, W2
MOV.w [W2++], W3
Indirect Direct Allowed
ADD.w W0, W1, [W2]
MOV.w W2, W3
Indirect Indirect Allowed
ADD.w W0, W1, [W2]
MOV.w [W2], W3
Indirect Indirect with
modification
Allowed
ADD.w W0, W1, [W2]
MOV.w [W2++], W3
Indirect with
modification
Direct Allowed
ADD.w W0, W1, [W2++]
MOV.w W2, W3
Indirect Indirect Stall
ADD.w W0, W1, [W2]
MOV.w [W2], W3
; W2=0x0004 (mapped W2)
Indirect Indirect with
modification
Stall
ADD.w W0, W1, [W2]
MOV.w [W2++], W3
; W2=0x0004 (mapped W2)
Indirect with
modification
Indirect Stall
ADD.w W0, W1, [W2++]
MOV.w [W2], W3
Indirect with
modification
Indirect with
modification
Stall
ADD.w W0, W1, [W2++]
MOV.w [W2++], W3

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