# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Motor Control PWM

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© 2010 Microchip Technology Inc. Preliminary DS39735A-page 47-45
Section 47. Motor Control PWM
Motor Control
PWM
47
47.15 OPERATION IN POWER-SAVING MODES
47.15.1 PWM Operation in Sleep Mode
When the device enters Sleep mode, the system clock is disabled. Since the clock for the
PWM time base is derived from the system clock source (T
CY), that clock will also be disabled.
All enabled PWM output pins will be frozen in the output states that were in effect prior to
entering Sleep mode.
If the PWM module is used to control a load in a power application, the PWM module outputs
must be placed into a safe state before executing the PWRSAV instruction. Depending on the
application, the load may begin to consume excessive current when the PWM outputs are
frozen in a particular output state. For example, the PxOVDCON register can be used to
manually turn off the PWM output pins, as shown in Example 47-9.
Example 47-9: Manually Placing PWM Pins Into an Inactive State
The Fault A and Fault B input pins, if enabled to control the PWM pins via the PxFLTACON and
PxFLTBCON registers, continue to function normally when the device is in Sleep mode. If one
of the Fault pins is driven low while the device is in Sleep mode, the PWM outputs are driven to
the programmed Fault states in the PxFLTACON and PxFLTBCON registers.
The Fault input pins can also wake the CPU from Sleep mode. If the Fault interrupt enable bit
is set (FLTxAIE = 1 or FLTxBIE = 1), the device will wake from Sleep mode when the Fault pin
is driven low. If the Fault pin interrupt priority is greater than the current CPU priority, program
execution starts at the Fault pin interrupt vector location upon wake-up. Otherwise, execution
continues from the next instruction following the PWRSAV instruction.
47.15.2 PWM Operation in Idle Mode
When the device enters Idle mode, the system clock sources remain functional and the CPU
stops executing code. The PWM module can optionally continue to operate in Idle mode. The
PWM Time Base Stop in Idle Mode (PTSIDL) bit in the PWM Time Base Control (PxTCON<13>)
register determines whether the PWM module stops in Idle mode or continues to operate
normally.
If PTSIDL = 0, the module operates normally when the device enters Idle mode. The PWM
time base interrupt, if enabled, can be used to wake the device from Idle mode. If the PWM
Time Base Interrupt Enable (PTIE) bit is set (PTIE = 1), the device will wake from Idle mode
when the PWM time base interrupt is generated. If the PWM time base interrupt priority is
greater than the current CPU priority, program execution starts at the PWM interrupt vector
location upon wake-up. Otherwise, execution will continue from the next instruction following
the PWRSAV instruction.
If PTSIDL = 1, the module stops in Idle mode. If the PWM module is programmed to stop in
Idle mode, the operation of the PWM outputs and Fault input pins is the same as the operation
in Sleep mode. (See Section 47.15.1 PWM Operation in Sleep Mode for details.)
; This code example drives all PWM1 pins to the inactive state
; before executing the PWRSAV instruction.
CLR P1OVDCON ; Force all PWM outputs inactive
PWRSAV #0 ; Put the device in Sleep mode
SETM.B P1OVDCONH ; Set the POVD bits when the device wakes up

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