# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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dsPIC33/PIC24 Family Reference Manual
DS70000195F-page 42  2007-2014 Microchip Technology Inc.
7.3.4 7-BIT ADDRESS AND SLAVE READ
When a slave read is specified by having R/W = 1 in a 7-bit address byte, the process of
detecting the device address is similar to that of a slave write, as illustrated in Figure 7-5. If the
addresses match, the following events occur:
• An ACK
is generated if the AHEN bit is clear
• The D/A
status bit is cleared and the R/W status bit is set
• The module generates the SI2CxIF interrupt on the falling edge of the ninth SCLx clock
Because the slave is expected to reply with data at this point, it is necessary to suspend the
operation of the I
2
C bus to allow the user software to prepare a response. This is done automatically
when the module clears the SCLREL bit. With SCLREL low, the slave will pull down the SCLx clock
line, causing a Wait on the I
2
C bus. The slave and the I
2
C bus remain in this state until the user
software writes the I2CxTRN register with the response data and sets the SCLREL bit.
Figure 7-5: Slave Read 7-Bit Address Detection Timing Diagram (AHEN = 0)
Note: For more information on the AHEN and DHEN bits, refer to section Section 7.3.3
“7-Bit Address and Slave Write with the AHEN and DHEN Bits”.
The SCLREL bit will automatically clear after detecting the slave read address,
irrespective of the state of the STREN bit.
SCLx (Master)
SDAx (Master)
SDAx (Slave)
SI2CxIF Interrupt
4 5
1
3
Detecting Start bit enables
1
I
2
C™ Bus State
(D) (D) (A)(D)
A5A6A7 A4 A3 A2 A1
D/A
ADD10
SCLREL
R/W
address detection. If SCIE
is set,
R/W
= 1 indicates that the slave
3
sends data bytes.
Valid address of first byte clears
4
D/A status bit. Slave generates ACK.
R/W
status bit is set. Slave generates 5
interrupt. SCLREL is cleared.
6
Bus waiting. Slave prepares to
6
send data.
SCLx (Slave)
Slave pulls SCLx low while
SCLREL = 0.
(S) (Q)
R/W = 1
2
2
User software clears the interrupt
flag.
Note 1: The SCIE bit may not be available in all the devices. Refer to the specific device data sheet for availability.
then interrupt will be asserted.
(1)

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