# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 -- Errata

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PIC24FJ64GA004 FAMILY
DS80000470H-page 12  2009-2013 Microchip Technology Inc.
26. Module: I
2
C
Bit and byte-based operations may not have the
intended affect on the I2CxSTAT register. It is
possible for bit and byte operations, performed on
the lower byte of I2CxSTAT, to clear the BCL bit
(I2CxSTAT<10>). Bit and byte operation per-
formed on the upper byte of I2CxSTAT, or on the
BCL bit directly, may not be able to clear the BCL
bit.
Work around
Modifications to the I2CxSTAT register should be
done using word writes only. This can be done in
‘C’ by always writing to the register itself and not
the individual bits. For example, the code,
I2C1STAT &= 0xFBFF, will force the compiler to
use a word-based operation to clear the BCL bit.
In assembly, it is done by not using BSET or BCLR
instructions, or instructions with the .b modifier.
Affected Silicon Revisions
27. Module: UART
When the UARTx is configured for IR interface
operations (UxMODE<9:8> = 11), the 16x baud
clock signal on the BCLK pin will only be present
when the module is transmitting. The pin will be
Idle at all other times.
Work around
Configure one of the output compare modules to
generate the required baud clock signal when the
UARTx is receiving data or in an Idle state.
Affected Silicon Revisions
28. Module: I/O (Peripheral Pin Select)
The remappable pin functions multiplexed to some
pins do not have a higher priority than fixed digital
signals assigned to those pins. By design, a
remapped digital function should always have
priority over any other fixed digital function on the
same pin.
Using these remappable and specific fixed digital
functions at the same time may cause conflicts
and unexpected results on:
• RP12 and PMD0
• RP18 and PMA2 (40-pin and 44-pin
devices only)
No other fixed digital functions are affected.
Work around
On the affected pins, enable either the remappable
peripherals, or the specific fixed digital peripherals,
but not both at the same time.
Affected Silicon Revisions
29. Module: UART (UERIF Interrupt)
The UARTx error interrupt may not occur, or occur
at an incorrect time, if multiple errors occur during
a short period of time.
Work around
Read the error flags in the UxSTA register when-
ever a byte is received to verify the error status. In
most cases, these bits will be correct, even if the
UARTx error interrupt fails to occur. For possible
exceptions, refer to Errata # 30.
Affected Silicon Revisions
A3/
A4
B4 B5
B8
X
A3/
A4
B4 B5
B8
X
A3/
A4
B4 B5 B8
X
A3/
A4
B4 B5
B8
X X X
X

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