# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Comparator with Blanking

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PIC24F Family Reference Manual
DS39741A-page 48-12 Preliminary © 2010 Microchip Technology Inc.
Register 48-5: CMxFLTR: Comparator Filter Control Register
U-0 U-0 U-0 U-0 U-0 U-0 U-0 I-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— CFSEL<2:0> CFLTREN CFDIV<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as ‘0’
bit 6-4 CFSEL<2:0>: Comparator Filter Input Clock Select bits
111 = Reserved
110 = Reserved
101 = Reserved
100 = Reserved
011 = Reserved
(1)
010 = Timer2 Match
(1)
001 = PWM Special Event Trigger
(1)
000 = Instruction Clock (FCY)
(1)
bit 3 CFLTREN: Comparator Output Digital Filter Enable bit
1 = Digital filter enabled
0 = Digital filter disabled
bit 2-0 CFDIV<2:0>: Comparator Output Filter Clock Divide Select bits
111 = Clock Divide 1:128
110 = Clock Divide 1:64
101 = Clock Divide 1:32
100 = Clock Divide 1:16
011 = Clock Divide 1:8
010 = Clock Divide 1:4
001 = Clock Divide 1:2
000 = Clock Divide 1:1
Note 1: For more information, refer to the specific device data sheet.

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