# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Oscillator

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© 2009 Microchip Technology Inc. DS39700C-page 6-7
Section 6. Oscillator
Oscillator
6
6.4.2 Clock Divider Register (CLKDIV)
The Clock Divider register (Register 6-2) controls the features associated with Doze mode, as
well as the postscaler for the FRC Oscillator.
The ROI bit (CLKDIV<15>) allows an interrupt to exit Doze mode and automatically selects a
1:1 ratio for the processor and peripheral clocks. The DOZEN bit (CLKDIV<11>) is cleared after
the exit from Doze mode. Clearing the ROI bit prevents interrupts from affecting Doze mode.
The DOZE bits (CLKDIV<14:12>) select the ratio of processor clocks to peripheral clocks. The
range is software-selectable between 1:1 to 1:128. The MCLR
and PORs default to the 1:1 ratio.
This feature allows the CPU to consume less power without disrupting the peripheral’s
operations.
Setting the DOZEN bit places the device into Doze mode and engages the processor clock
postscaler. This bit is cleared when the ROI bit is set and an interrupt occurs.
The RCDIV bits (CLKDIV<10:8>) select the postscaler option for the FRC Oscillator output, allow-
ing users to choose a lower clock frequency than the nominal 8 MHz. This option is described in
more detail in Section 6.8.2 “FRC Postscaler Mode (FRCDIV)” and Section 6.8.3 “FRC Oscil-
lator with PLL Mode (FRCPLL)”.
For PIC24F devices featuring USB functionality (for example, the PIC24FJ256GB110 family), the
CPDIV<1:0> bits (CLKDIV<7:6>) select the system clock speed when the USB module is
enabled and active. Their function is covered in more detail in Section 6.6.2 “96 MHz PLL
Block”.
Where available, the PLLEN bit (CLKDIV<5>) enables the 96 MHz PLL module that generates
the 96 MHz clock source for USB and graphics controller modules. The G1CLKSEL bit
(CLKDIV<4>) further selects the clock source for the graphics controller module. This selection
is also described in Section 6.6.2 “96 MHz PLL Block”.
bit 3 CF: Clock Fail Detect bit
1 = FSCM has detected a clock failure
0 = No clock failure has been detected
bit 2 POSCEN: Primary Oscillator Sleep Enable bit
(4)
1 = Primary Oscillator continues to operate during Sleep mode
0 = Primary Oscillator is disabled during Sleep mode
bit 1 SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit
1 = Enable Secondary Oscillator
0 = Disable Secondary Oscillator
bit 0 OSWEN: Oscillator Switch Enable bit
1 = Initiate an oscillator switch to the clock source specified by the NOSC<2:0> bits
0 = Oscillator switch is complete
Register 6-1: OSCCON: Oscillator Control Register (Continued)
Note 1: Reset values for these bits are determined by the FNOSC Configuration bits.
2: IOLOCK is available only on devices with Peripheral Pin Select; refer to the particular device data sheet for
more information. IOLOCK can only be changed once an unlocking sequence has been executed. In
addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared.
3: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected.
4: POSCEN is only available on select device families; refer to the particular device data sheet for more
information.

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