# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 8 © 2005-2011 Microchip Technology Inc.
1.5 INSTRUCTION SET SYMBOLS
The summary tables in Section 3.2 “Instruction Set Overview” and Section 7.2 “Instruction
Set Summary Table”, and the instruction descriptions in Section 5.4 “Instruction
Descriptions” utilize the symbols shown in Table 1-2.
Table 1-2: Symbols Used in Instruction Summary Tables and Descriptions
Symbol
(1)
Description
{ }
Optional field or operation
[text] The location addressed by text
(text) The contents of text
#text The literal defined by text
a ∈ [b, c, d] “a” must be in the set of [b, c, d]
<n:m> Register bit field
{label:} Optional label name
Acc Accumulator A or Accumulator B
AWB Accumulator Write Back
bit4 4-bit wide bit position (0:7 in Byte mode, 0:15 in Word mode)
Expr Absolute address, label or expression (resolved by the linker)
f File register address
lit1 1-bit literal (0:1)
lit4 4-bit literal (0:15)
lit5 5-bit literal (0:31)
lit8 8-bit literal (0:255)
lit10 10-bit literal (0:255 in Byte mode, 0:1023 in Word mode)
lit14 14-bit literal (0:16383)
lit16 16-bit literal (0:65535)
lit23 23-bit literal (0:8388607)
Slit4 Signed 4-bit literal (-8:7)
Slit6 Signed 6-bit literal (-32:31) (range is limited to -16:16)
Slit10 Signed 10-bit literal (-512:511)
Slit16 Signed 16-bit literal (-32768:32767)
TOS Top-of-Stack
Wb Base working register
Wd Destination working register (direct and indirect addressing)
Wdo Destination working register (direct and indirect addressing, including indirect addressing with offset)
Wm, Wn Working register divide pair (dividend, divisor)
Wm * Wm Working register multiplier pair (same source register)
Wm * Wn Working register multiplier pair (different source registers)
Wn Both source and destination working register (direct addressing)
Wnd Destination working register (direct addressing)
Wns Source working register (direct addressing)
WREG Default working register (assigned to W0)
Ws Source working register (direct and indirect addressing)
Wso Source working register (direct and indirect addressing, including indirect addressing with offset)
Wx Source Addressing mode and working register for X data bus prefetch
Wxd Destination working register for X data bus prefetch
Wy Source Addressing mode and working register for Y data bus prefetch
Wyd Destination working register for Y data bus prefetch
Note 1: The range of each symbol is instruction dependent. Refer to
Section 5. “Instruction Descriptions” for
the specific instruction range.

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