# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Serial Peripheral Interface

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© 2007 Microchip Technology Inc. Advance Information DS39699B-page 23-10
Section 23. Serial Peripheral Interface (SPI)
Serial Peripheral
Interface (SPI)
23
23.3.2.1 MASTER MODE
In Standard Master mode, the system clock is prescaled and then used as the serial clock. The
prescaling is based on the settings in the PPRE1:PPRE0 (SPIxCON1<1:0>) and SPRE2:SPRE0
(SPIxCON1<4:2>) bits. The serial clock is output via the SCKx pin to slave devices. Clock
pulses are only generated when there is data to be transmitted. For further information, refer to
Section 23.4 “SPI Master Mode Clock Frequency”. The CKP and CKE bits determine, on
which edge of the clock, data transmission occurs.
Both data to be transmitted and data that is received are respectively written into, or read from,
the SPIxBUF register.
The following describes the SPIx module operation in Master mode:
1. Once the module is set up for Master mode of operation and enabled, data to be
transmitted is written to the SPIxBUF register. The SPIxTBF (SPIxSTAT<1>) bit is set.
2. The contents of SPIxTXB are moved to the Shift register, SPIxSR, and the SPIxTBF bit is
cleared by the module.
3. A series of 8/16 clock pulses shifts out 8/16 bits of transmit data from the SPIxSR to the
SDOx pin and simultaneously shifts in the data at the SDIx pin into the SPIxSR.
4. When the transfer is complete, the following events will occur:
• The interrupt flag bit, SPIxIF, is set. SPIx interrupts can be enabled by setting the
interrupt enable bit, SPIxIE. The SPIxIF flag is not cleared automatically by the
hardware.
• Also, when the ongoing transmit and receive operation is completed, the contents of
the SPIxSR are moved to the SPIxRXB register.
• The SPIxRBF (SPIxSTAT<0>) bit is set by the module, indicating that the receive
buffer is full. Once the SPIxBUF register is read by the user code, the hardware clears
the SPIxRBF bit.
5. If the SPIxRBF bit is set (receive buffer is full) when the SPIx module needs to transfer
data from SPIxSR to SPIxRXB, the module will set the SPIROV (SPIxSTAT<6>) bit,
indicating an overflow condition.
6. Data to be transmitted can be written to SPIxBUF by the user software at any time as long
as the SPIxTBF (SPIxSTAT<1>) bit is clear. The write can occur while SPIxSR is shifting
out the previously written data, allowing continuous transmission.
To set up the SPIx module for the Master mode of operation:
1. If using interrupts:
• Clear the SPIxIF bit in the respective IFSn register.
• Set the SPIxIE bit in the respective IECn register.
• Write the SPIxIP bits in the respective IPCn register to set the interrupt priority.
2. Write the desired settings to the SPIxCON register with MSTEN (SPIxCON1<5>) = 1.
3. Clear the SPIROV bit (SPIxSTAT<6>).
4. Enable SPIx operation by setting the SPIEN bit (SPIxSTAT<15>).
5. Write the data to be transmitted to the SPIxBUF register. Transmission (and reception) will
start as soon as data is written to the SPIxBUF register.
23.3.2.1.1 External Clocking in Master Mode
In Standard Master mode, the module can also be configured to operate with an external data
clock. SPIx clock operation is controlled by the DISSCK bit (SPIxCON1<12>). When this bit is
set, the internal data clock is disabled and data is transferred when external clock pulses are
presented on the SCKx pin. All other aspects of Standard Master mode operation are the same
as before.
Note: The SPIxSR register cannot be written into directly by the user. All writes to the
SPIxSR register are performed through the SPIxBUF register.
Note: The DISSCK bit is available only in SPI Master modes.

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