# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Family Data Sheet

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© 2011-2012 Microchip Technology Inc. Preliminary DS39997C-page 25
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
3.0 CPU
The PIC24FJ16MC101/102 and PIC24FJ32MC101/
102/104 CPU module has a 16-bit (data) modified
Harvard architecture with an enhanced instruction set
and addressing modes. The CPU has a 24-bit
instruction word with a variable length opcode field.
The Program Counter (PC) is 23 bits wide and
addresses up to 4M by 24 bits of user program memory
space. The actual amount of program memory
implemented varies by device. A single-cycle
instruction prefetch mechanism is used to help
maintain throughput and provides predictable
execution. All instructions execute in a single cycle,
with the exception of instructions that change the
program flow, the double-word move (MOV.D)
instruction and the table instructions. Overhead-free,
single-cycle program loop constructs are supported
using the REPEAT instruction, which is interruptible at
any point.
The PIC24FJ16MC101/102 and PIC24FJ32MC101/102/
104 devices have sixteen, 16-bit working registers in the
programmer’s model. Each of the working registers can
serve as a data, address or address offset register. The
16th working register (W15) operates as a software Stack
Pointer (SP) for interrupts and calls.
The PIC24FJ16MC101/102 and PIC24FJ32MC101/
102/104 instruction set includes many addressing
modes and is designed for optimum C compiler
efficiency. For most instructions, PIC24FJ16MC101/
102 and PIC24FJ32MC101/102/104 devices are
capable of executing a data (or program data) memory
read, a working register (data) read, a data memory
write, and a program (instruction) memory read per
instruction cycle. As a result, three parameter
instructions can be supported, allowing A + B = C
operations to be executed in a single cycle.
A block diagram of the CPU is shown in Figure 3-1,
and the programmer’s model for the
PIC24FJ16MC101/102 and PIC24FJ32MC101/102/
104 is shown in Figure 3-2.
3.1 Data Addressing Overview
The data space can be linearly addressed as 32K words
or 64 Kbytes using an Address Generation Unit (AGU).
The upper 32 Kbytes of the data space memory map can
optionally be mapped into program space at any 16K
program word boundary defined by the 8-bit Program
Space Visibility Page register (PSVPAG). The program to
data space mapping feature lets any instruction access
program space as if it were data space.
3.2 Special MCU Features
The PIC24FJ16MC101/102 and PIC24FJ32MC101/
102/104 features a 17-bit by 17-bit, single-cycle
multiplier. The multiplier can perform signed, unsigned
and mixed-sign multiplication. Using a 17-bit by 17-bit
multiplier for 16-bit by 16-bit multiplication makes
mixed-sign multiplication possible.
The PIC24FJ16MC101/102 and PIC24FJ32MC101/
102/104 supports 16/16 and 32/16 integer divide
operations. All divide instructions are iterative
operations. They must be executed within a REPEAT
loop, resulting in a total execution time of 19 instruction
cycles. The divide operation can be interrupted during
any of those 19 cycles without loss of data.
A multi-bit data shifter is used to perform up to a 16-bit,
left or right shift in a single cycle.
Note 1: This data sheet summarizes the features
of the PIC24FJ16MC101/102 and
PIC24FJ32MC101/102/104 family of
devices. However, it is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 2. “CPU”
(DS39703) in the “PIC24F Family Refer-
ence Manual”, which is available from the
Microchip web site (www.microchip.com).
2: It is important to note that the
specifications in Section 26.0 “Electri-
cal Characteristics” of this data sheet,
supercede any specifications that may be
provided in PIC24F Family Reference
Manual sections.
3: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.

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