# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 -- Serial Peripheral Interface

- 1
- 2
- 3
- 4
- 5
- 6
- 7
…
- 41
- 42

 2014 Microchip Technology Inc. DS70005185A-page 5
Serial Peripheral Interface (SPI) Module
2.0 SPI REGISTERS
This section outlines the specific functions of each register that controls the operation of the
SPIx module.
• SPIxSTAT: SPIx Status and Control Register
- Indicates the various status conditions, such as receive overflow, transmit buffer full
and receive buffer full
- Specifies the operation of the SPIx module during Idle mode
- Contains a bit that can enable or disable the SPIx module
• SPIxCON1: SPIx Control Register 1
- Specifies the clock prescaler, Master/Slave mode, Word/Byte communication, clock
polarity and clock/data pin operation
• SPIxCON2: SPIx Control Register 2
- Enables or disables the Enhanced Buffer and Framed SPI mode operation
- Specifies the frame synchronization pulse direction, polarity and edge selection
• SPIxBUF: SPIx Data Receive/Transmit Buffer Register
- In Standard mode, the register consists of two separate internal registers: the SPIx
Transmit Buffer (SPIxTXB) register and the SPIx Receive Buffer (SPIxRXB) register
- The SPIxTXB and the SPIxRXB are unidirectional, 16-bit registers that share the SFR
address of the SPIxBUF register. If the user application writes data to be transmitted to
the SPIxBUF register, internally the data is written to the SPIxTXB register. Similarly,
when the user application reads the received data from the SPIxBUF register,
internally the data is read from the SPIxRXB register.
- When the enhanced buffer is enabled, the SPIxBUF register becomes the data inter-
face to two 8-level FIFOs: one for reception and another for transmission. Each buffer
can hold up to eight pending data transfers. When the CPU writes data to the SPIxBUF
register, the data is moved into the next transmit buffer location. The SPIx peripheral
begins to transfer data after the first CPU writes to the SPIxBUF register and continues
until all pending transfers are completed. After each transfer, the SPIx updates the
next receive buffer location with the received data and is available for the CPU to read.
After the CPU read, the data is read from the next receive buffer location.
- The double-buffer transmit/receive operation allows continuous data transfer in the
background; the transmission and reception occur simultaneously.
- In addition, there is an internal 16-bit SPIx Shift register (SPIxSR) that is not
memory-mapped; it shifts data in and out of the SPI port.

- 1
- 2
- 3
- 4
- 5
- 6
- 7
…
- 41
- 42