# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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© 2005-2011 Microchip Technology Inc. DS70157F-page 433
Section 5. Instruction Descriptions
Instruction
Descriptions
5
TBLWTL Table Write Low
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} TBLWTL{.B} Ws, [Wd]
[Ws], [Wd++]
[Ws++], [Wd--]
[Ws--], [++Wd]
[++Ws], [--Wd]
[--Ws],
Operands: Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]
Operation: For byte operation:
If (LSB(Wd)=1)
(Ws) → Program Mem [(TBLPAG),(Wd)] <15:8>
Else
(Ws) → Program Mem [(TBLPAG),(Wd)] <7:0>
For word operation:
(Ws) → Program Mem [(TBLPAG),(Wd)] <15:0>
Status Affected: None
Encoding: 1011 1011 0Bqq qddd dppp ssss
Description: Store the contents of the working source register Ws to the least significant
word of program memory. The destination word address of program
memory is formed by concatenating the 8-bit Table Pointer register,
TBLPAG<7:0>, with the effective address specified by Wd. Either direct or
indirect addressing may be used for Ws, and indirect addressing must be
used for Wd.
In Word mode, Ws is stored to the lower 2 bytes of program memory. In
Byte mode, the Least Significant bit of Wd determines the destination byte.
If Wd is not word-aligned, Ws is stored to the second byte of program
memory (PM<15:8>). If Wd is word-aligned, Ws is stored to the first byte of
program memory (PM<7:0>).
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note: The extension .B in the instruction denotes a byte move rather
than a word move. You may use a .W extension to denote a word
move, but it is not required.
Words: 1
Cycles:
2
(1)
Note 1:
In dsPIC33E and PIC24E devices, the listed cycle count does not apply to read and
read-modify-write operations on non-CPU Special Function Registers. For more
details, see
Note 3
in
Section 3.2.1 “Multi-Cycle Instructions”
.

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