# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- 10-Bit ADC

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© 2010 Microchip Technology Inc. Preliminary DS39737A-page 49-5
Section 49. 10-Bit ADC with 4 Simultaneous Conversions
10-Bit ADC with
4 Simultaneous
Conversions
49
Register 49-1: ADxCON1: ADCx Control Register 1
R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0
ADON
— ADSIDL — — — FORM1 FORM0
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
HC,HS
R/C-0
HC, HS
SSRC2 SSRC1 SSRC0
— SIMSAM ASAM SAMP DONE
bit 7 bit 0
Legend: HC = Hardware Clearable bit HS = Hardware Settable bit C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ADON: ADC Operating Mode bit
1 = ADC module is operating
0 = ADC is off
bit 14 Unimplemented: Read as ‘0’
bit 13 ADSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12-10 Unimplemented: Read as ‘0’
bit 9-8 FORM<1:0>: Data Output Format bits
11 = Signed fractional (D
OUT = sddd dddd dd00 0000, where s = sign, d = data)
10 = Fractional (D
OUT = dddd dddd dd00 0000)
01 = Signed integer (D
OUT = ssss sssd dddd dddd, where s = sign, d = data)
00 = Integer (D
OUT = 0000 00dd dddd dddd)
bit 7-5 SSRC<2:0>: Sample Clock Source Select bits
111 = Internal counter ends sampling and starts conversion (auto-convert)
110 = Reserved
101 = Reserved
100 = Reserved
011 = Motor control PWM1 interval ends sampling and starts conversion
010 = GP Timer3 compare ends sampling and starts conversion
001 = Active transition on INT0 pin ends sampling and starts conversion
000 = Clearing sample bit ends sampling and starts conversion
bit 4 Unimplemented: Read as ‘0’
bit 3 SIMSAM: Simultaneous Sample Select bit (only applicable when CHPS<1:0> = 01 or 1x)
1 = Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x) or samples CH0 and CH1
simultaneously (when CHPS<1:0> = 01)
0 = Samples multiple channels individually in sequence
bit 2 ASAM: ADC Sample Auto-Start bit
1 = Sampling begins immediately after the last conversion; SAMP bit is auto-set
0 = Sampling begins when the SAMP bit is set
bit 1 SAMP: ADC Sample Enable bit
1 = ADC S&H amplifiers are sampling
0 = ADC S&H amplifiers are holding
If ASAM = 0, software can write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1.
If SSRC = 000, software can write ‘0’ to end sampling and start conversion. If SSRC 000,
automatically cleared by hardware to end sampling and start conversion.
bit 0 DONE: ADC Conversion Status bit
1 = ADC conversion cycle is completed
0 = ADC conversion not started or in progress
Automatically set by hardware when the A/D conversion is complete. Software can write ‘0’ to clear the
DONE status bit (software not allowed to write ‘1’). Clearing this bit does NOT affect any operation in
progress. Automatically cleared by hardware at the start of a new conversion.

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