# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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© 2005-2011 Microchip Technology Inc. DS70157F-page 39
Section 3. Instruction Set Overview
Instruction Set
Overview
3
3.2.1 Multi-Cycle Instructions
As the instruction summary tables show, most instructions execute in a single cycle, with the
following exceptions:
• Instructions DO, MOV.D, POP.D, PUSH.D, TBLRDH, TBLRDL, TBLWTH and
TBLWTL require 2 cycles to execute
• Instructions DIV.S, DIV.U and DIVF are single-cycle instructions, which should be
executed 18 consecutive times as the target of a REPEAT instruction
• Instructions that change the program counter also require 2 cycles to execute, with the
extra cycle executed as a NOP. Compare-skip instructions, which skip over a 2-word
instruction, require 3 instruction cycles to execute, with 2 cycles executed as a NOP.
Compare-branch instructions (dsPIC33E/PIC24E devices only) require 5 instruction cycles
to execute when the branch is taken.
• The RETFIE, RETLW and RETURN are a special case of an instruction that changes the
program counter. These execute in 3 cycles, unless an exception is pending and then they
execute in 2 cycles.
3.2.2 Multi-Word Instructions
As defined by Table 3-2, almost all instructions consume one instruction word (24 bits), with the
exception of the CALL, DO and GOTO instructions, which are Program Flow Instructions, listed
in Table 3-8. These instructions require two words of memory because their opcodes embed
large literal operands.
Note: The DO and DIVF instructions are only available in the dsPIC30F, dsPIC33F, and
dsPIC33E device families.
Note 1: Instructions which access program memory as data, using Program Space Visibility
(PSV), will incur a one or two cycle delay for PIC24F, PIC24H, dsPIC30F, and
dsPIC33F devices, whereas using PSV in dsPIC33E and PIC24E devices incurs a
4-cycle delay based on Flash memory access time. However, regardless of which
device is being used, when the target instruction of a REPEAT loop accesses
program memory as data, only the first execution of the target instruction is subject
to the delay. See the specific device family reference manual for details.
2: All instructions may incur an additional delay on some device families, depending
on Flash memory access time. For example, PIC24E and dsPIC33E devices have
a 3-cycle Flash memory access time. However, instruction pipelining increases the
effective instruction execution throughput. Refer to Section 2. “CPU” of the
specific device family reference manual for details on instruction timing.
3: All read and read-modify-write operations (including bit operations) on non-CPU
Special Function Registers (e.g., I/O Port, peripheral control, or status registers;
interrupt flags, etc.) in PIC24E and dsPIC33E devices require 2 instruction cycles
to execute. However, all write operations on both CPU and non-CPU Special
Function Registers, and all read and read-modify-write operations on CPU Special
Function Registers require 1 instruction cycle.

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