# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Motor Control PWM

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PIC24F Family Reference Manual
DS39735A-page 47-12 Preliminary © 2010 Microchip Technology Inc.
Register 47-9: PxFLTACON: Fault A Control Register
(1)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
  FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L
bit 15 bit 8
R/W-0 U-0 U-0 U-0 U-0 R/W-x
(2)
R/W-x
(2)
R/W-x
(2)
FLTAM     FAEN3 FAEN2 FAEN1
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as 0
bit 13-8 FAOV3H:FAOV1L: Fault Input A PWM Override Value bits
1 = PWM output pin is driven active on an external Fault input event
0 = PWM output pin is driven inactive on an external Fault input event
bit 7 FLTAM: Fault A Mode bit
1 = Fault A input pin functions in Cycle-by-Cycle mode
0 = Fault A input pin latches all control pins to the programmed states in PxFLTACON<15:8>
bit 6-3 Unimplemented: Read as 0
bit 2 FAEN3: Fault Input A Enable bit
(2)
1 = PWMxH3/PWMxL3 pin pair is controlled by Fault Input A
0 = PWMxH3/PWMxL3 pin pair is not controlled by Fault Input A
bit 1 FAEN2: Fault Input A Enable bit
(2)
1 = PWMxH2/PWMxL2 pin pair is controlled by Fault Input A
0 = PWMxH2/PWMxL2 pin pair is not controlled by Fault Input A
bit 0 FAEN1: Fault Input A Enable bit
(2)
1 = PWMxH1/PWMxL1 pin pair is controlled by Fault Input A
0 = PWMxH1/PWMxL1 pin pair is not controlled by Fault Input A
Note 1: In devices where the PWMLOCK bit is present in the FOSCSEL Configuration register, this register can be
write-protected. If the PWMLOCK input signal is asserted (PWMLOCK = 1), the PxFLTACON register is
writable only after the proper sequence is written to the PWMKEY register. If the PWMLOCK input signal is
deasserted (PWMLOCK = 0), the PxFLTACON register is writable at all times. Refer to Section 47.14.4
Write-Protected Registers for further details about the unlock sequence.
2: In devices where the PWMLOCK bit is present in the FOSCSEL Configuration register, the Reset value for
this bit is 1 when PWMLOCK is set to 1. In all other configurations, the Reset value for this bit is 0.
Refer to the specific device data sheet for further details.

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