# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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dsPIC33/PIC24 Family Reference Manual
DS70000195F-page 50  2007-2014 Microchip Technology Inc.
7.4.1 ACKNOWLEDGE GENERATION
Normally, the slave Acknowledges all the received bytes by sending an ACK on the ninth SCLx
clock. If the receive buffer is overrun, the slave does not generate this ACK
. The overrun is
indicated if either (or both) of the following occur:
• The Receive Buffer Full bit, RBF (I2CxSTAT<1>), was set before the transfer was received
• The Receive Overflow bit, I2COV (I2CxSTAT<6>), was set before the transfer was received
Table 7-3 shows what happens when a data transfer byte is received, given the status of the RBF
and I2COV status bits. If the RBF status bit is already set when the slave attempts to transfer to
the I2CxRCV register, the transfer does not occur, but the interrupt is generated and the I2COV
status bit is set. If both the RBF and I2COV status bits are set, the slave acts similarly. The
shaded cells show the condition where user software did not properly clear the overflow
condition.
Reading the I2CxRCV register clears the RBF status bit. The I2COV status bit is cleared by
writing to a ‘0’ through user software.
7.4.2 RECEIVE BUFFER OVERWRITE (I
2
C SLAVE MODE ONLY)
If the BOEN bit (I2CxCONH<4>) is set, then the I2COV bit (I2CxSTAT<6>) is ignored. If the RBF
bit (I2CxSTAT<1>) is not set, then the ACK
is generated for the receive address or data; the
I2CxRCV buffer is updated with I2CxRSR.
Table 7-3: Data Transfer Received Byte Actions
7.4.3 WAIT STATES DURING SLAVE RECEPTIONS
When the slave receives a data byte, the master can potentially begin sending the next byte
immediately. This allows the user software controlling the nine slave SCLx clock periods to
process the previously received byte. If this is not enough time, the slave software may want to
generate a bus Wait period.
The STREN bit (I2CxCON<6> or I2CxCONL<6>) enables a bus Wait to occur on slave
receptions. When STREN = 1 at the falling edge of the ninth SCLx clock of a received byte, the
slave clears the SCLREL bit. Clearing the SCLREL bit causes the slave to pull the SCLx line low,
initiating a Wait. The SCLx clock of the master and slave will synchronize, as provided in
Section 6.2 “Master Clock Synchronization”.
When the user software is ready to resume reception, the user software sets the SCLREL bit.
This causes the slave to release the SCLx line and the master resumes clocking.
Note: If the BOEN bit (I2CxCONH<4>) is set, then the I2COV bit (I2CxSTAT<6>) is
ignored and only the RBF bit (I2CxSTAT<1>) determines whether the module will
Acknowledge the message or not.
Status Bits as Data Byte
Received
Transfer
I2CxRSR to
I2CxRCV
Generate
ACK
Generate SI2CxIF
Interrupt
(interrupt occurs
if enabled)
Set
RBF
Set
I2COV
BOEN
(1)
RBF I2COV
x 0 0 Yes Yes Yes Yes No change
x 1 0 No No Yes No change Yes
x 1 1 No No Yes No change Yes
0 0 1 Yes No Yes Yes No change
1 0 1 Yes Yes Yes Yes No change
Legend: Shaded cells show states where the user software did not properly clear the
overflow condition.
Note 1: BOEN is not available on all the devices. Refer to the specific device data sheet for
availability.

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