# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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 2007-2014 Microchip Technology Inc. DS70000195F-page 23
Inter-Integrated Circuit™ (I
2
C™)
5.2.1 SENDING A 7-BIT ADDRESS TO THE SLAVE
Sending a 7-bit device address involves sending one byte to the slave. A 7-bit address byte must
contain the 7 bits of the I
2
C device address and a R/W status bit that defines whether the
message will be a write to the slave (master transmission and slave reception) or a read from the
slave (slave transmission and master reception).
5.2.2 STRICT SUPPORT IN MASTER MODE
The master device is allowed to generate an address that falls in the reserved address space if
the STRICT (I2CxCONL<11>) bit is set. For more information on the reserved address, refer to
Table 7-2.
5.2.3 SENDING A 10-BIT ADDRESS TO THE SLAVE
Sending a 10-bit device address involves sending two bytes to the slave. The first byte contains 5 bits
of the I
2
C device address reserved for 10-Bit Addressing modes and 2 bits of the 10-bit address. As
the next byte, which contains the remaining 8 bits of the 10-bit address, must be received by the slave,
the R/W status bit in the first byte must be ‘0’, indicating master transmission and slave reception. If
the message data is also directed toward the slave, the master can continue sending data. However,
if the master expects a reply from the slave, a Repeated Start sequence with the R/W
status bit at ‘1’
will change the R/W
state of the message to a read of the slave.
5.2.4 RECEIVING ACKNOWLEDGE FROM THE SLAVE
On the falling edge of the eighth SCLx clock, the TBF status bit is cleared and the master will
deassert the SDAx pin, allowing the slave to respond with an Acknowledge. The master will then
generate a ninth SCLx clock.
This allows the slave device being addressed to respond with an ACK
bit during the ninth bit time
if an address match occurs or data was received properly. A slave sends an Acknowledge when
it has recognized its device address (including a general call) or when the slave has properly
received its data.
The status of ACK
is written into the ACKSTAT bit (I2CxSTAT<15>) on the falling edge of the
ninth SCLx clock. After the ninth SCLx clock, the module generates the MI2CxIF interrupt and
enters into the Idle state until the next data byte is loaded into the I2CxTRN register.
5.2.5 ACKSTAT STATUS FLAG
The ACKSTAT bit (I2CxSTAT<15>) is cleared when the slave has sent an Acknowledge
(ACK
= 0) and is set when the slave does not Acknowledge (ACK = 1).
5.2.6 TBF STATUS FLAG
When transmitting, the TBF status bit (I2CxSTAT<0>) is set when the CPU writes to the I2CxTRN
register and is cleared when all 8 bits are shifted out.
5.2.7 IWCOL STATUS FLAG
If the user software attempts to write to the I2CxTRN register when a transmit is already in
progress (that is, the module is still shifting a data byte), the IWCOL status bit (I2CxSTAT<7>) is
set and the contents of the buffer are unchanged (the write does not occur). The IWCOL status
bit must be cleared in the user software.
Note: In a 7-Bit Addressing mode, each node using the I
2
C protocol should be configured
with a unique address that is stored in the I2CxADD register.
While transmitting the address byte, the master must shift the address bits<7:0>,
left by 1 bit, and configure bit 0 as the R/W
bit.
Note: In a 10-Bit Addressing mode, each node using the I
2
C protocol should be configured
with a unique address that is stored in the I2CxADD register.
While transmitting the first address byte, the master must shift the bits<9:8>, left
by one bit, and configure bit 0 as the R/W bit.
Note: Because queuing of events is not allowed, writing to the lower 5 bits of the I2CxCON
or I2CxCONL register is disabled until the transmit condition is complete.

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