# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA0XX -- Flash Programming Specification

- 1
- 2
…
- 12
- 13
- 14
- 15
- 16
…
- 51
- 52

PIC24FJXXXGA0XX
DS39768D-page 14 © 2008 Microchip Technology Inc.
3.2.2 REGOUT SERIAL INSTRUCTION
EXECUTION
The REGOUT control code allows for data to be
extracted from the device in ICSP mode. It is used to
clock the contents of the VISI register, out of the device,
over the PGDx pin. After the REGOUT control code is
received, the CPU is held Idle for 8 cycles. After these
8 cycles, an additional 16 cycles are required to clock the
data out (see Figure 3-3).
The REGOUT code is unique because the PGDx pin is
an input when the control code is transmitted to the
device. However, after the control code is processed,
the PGDx pin becomes an output as the VISI register is
shifted out.
FIGURE 3-3: REGOUT SERIAL EXECUTION
Note 1: After the contents of VISI are shifted out,
the PIC24FJXXXGA0XX device
maintains PGDx as an output until the
first rising edge of the next clock is
received.
2: Data changes on the falling edge and
latches on the rising edge of PGCx. For
all data transmissions, the Least
Significant bit (LSb) is transmitted first.
1 2 3 4 1 2 7 8
PGCx
P4
PGDx
PGDx = Input
Execute Previous Instruction,
CPU Held in Idle
Shift Out VISI Register<15:0>
P5
PGDx = Output
1 2 3 1 2 3 4
P4A
11 13 15 161412
No Execution Takes Place,
Fetch Next Control Code
0
0 0 0 0
PGDx = Input
MSb
1 2 3 4
1
4 5 6
LSb
141312
...
1110 0
Fetch REGOUT Control Code
0

- 1
- 2
…
- 12
- 13
- 14
- 15
- 16
…
- 51
- 52