# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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dsPIC33/PIC24 Family Reference Manual
DS70000195F-page 10  2007-2014 Microchip Technology Inc.
bit 5 ACKDT: Acknowledge Data bit (I
2
C Master mode; receive operation only)
Value that will be transmitted when the user software initiates an Acknowledge sequence.
1 = Sends a NACK during an Acknowledge
0 = Sends an ACK
during an Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit (I
2
C Master mode receive operation)
1 = Initiates the Acknowledge sequence on the SDAx and SCLx pins and transmits the ACKDT data bit
(hardware clears at the end of the master Acknowledge sequence)
0 = Acknowledge sequence is not in progress
bit 3 RCEN: Receive Enable bit (I
2
C Master mode)
1 = Enables Receive mode for I
2
C (hardware clears at the end of eighth bit of master receive data byte)
0 = Receive sequence is not in progress
bit 2 PEN: Stop Condition Enable bit (I
2
C Master mode)
1 = Initiates the Stop condition on the SDAx and SCLx pins (hardware clears at the end of master Stop
sequence)
0 = Stop condition is not in progress
bit 1 RSEN: Repeated Start Condition Enable bit (I
2
C Master mode)
1 = Initiates the Repeated Start condition on the SDAx and SCLx pins (hardware clears at the end of
master Repeated Start sequence)
0 = Repeated Start condition is not in progress
bit 0 SEN: Start Condition Enable bit (I
2
C Master mode)
1 = Initiates the Start condition on the SDAx and SCLx pins (hardware clears at the end of master Start
sequence)
0 = Start condition is not in progress
Register 3-1: I2CxCON: I2Cx Control Register (Continued)
Note 1: The IPMIEN bit should not be set when the I
2
C module is operating as a master.

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