# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 274 © 2005-2011 Microchip Technology Inc.
LSR
Logical Shift Right by Wns
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} LSR Wb, Wns, Wnd
Operands: Wb ∈ [W0 ... W15]
Wns ∈ [W0 ...W15]
Wnd ∈ [W0 ... W15]
Operation: Wns<4:0> → Shift_Val
0 → Wnd<15:15-Shift_Val + 1>
Wb<15:Shift_Val> → Wnd<15 - Shift_Val:0>
Status Affected: N, Z
Encoding:
1101 1110 0www wddd d000 ssss
Description: Logical shift right the contents of the source register Wb by the 5 Least
Significant bits of Wns (only up to 15 positions) and store the result in the
destination register Wnd. Direct addressing must be used for Wb and
Wnd.
The ‘w’ bits select the address of the base register.
The ‘d’ bits select the destination register.
The ‘s’ bits select the source register.
Note 1: This instruction operates in Word mode only.
2: If Wns is greater than 15, Wnd will be loaded with 0x0.
Words: 1
Cycles: 1
Example 1:
LSR W0, W1, W2 ; LSR W0 by W1
; Store result to W2
Before
Instruction
After
Instruction
W0 C00C W0 C00C
W1 0001 W1 0001
W2 2390 W2 6006
SR 0000 SR 0000
Example 2:
LSR W5, W4, W3 ; LSR W5 by W4
; Store result to W3
Before
Instruction
After
Instruction
W3 DD43 W3 0000
W4 000C W4 000C
W5 0800 W5 0800
SR 0000 SR 0002 (Z = 1)

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