# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 -- UART

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 2009-2013 Microchip Technology Inc. DS70000582E-page 31
UART
10.0 UART OPERATION WITH DMA
On some dsPIC33 and PIC24 devices, the Direct Memory Access (DMA) module can be used
to transfer data between the CPU and UART without CPU assistance. Refer to the specific
device data sheet to see if DMA is present on your particular device. For more information on the
DMA module, refer to the Direct Memory Access (DMA) FRM that pertains to the specific device
being used.
10.1 UART Receive with DMA
If the DMA channel is associated with the UART receiver, the UART should issue a DMA request
every time there is a character ready to be moved from the UART module to RAM. The DMA
transfers data from the UxRXREG register into RAM and issues a CPU interrupt after a pre-
defined number of transfers. As the DMA channels are unidirectional, the UART receive
operation would require one DMA channel.
The UART module must be configured to generate interrupts for every character received. For
the UART receiver to generate an RX interrupt for each character received, the UART Receive
Interrupt Mode Selection bits (URXISEL<1:0>) must be set to 00 or 01 in the Status and Con-
trol register (UxSTA). When the UART and DMA channel are properly configured, the UART
receiver issues a DMA request as soon as data is received. No special steps need to be taken
by the user application to initiate a DMA transfer.
While configuring for UART reception, the word size of the DMA channel should be set to 16-bit.
This configures the DMA channel to read 16 bits from the UART module when data is available to
be read. The lower byte of the data represents the actual data byte received by the UART module.
The upper byte contains the UART status when the byte was received. Note that the reading of the
UxSTA register, when the UART reception is DMA enabled, will not return the status of the FERR
and PERR bits. This status is available in the upper byte of the 16-bit word that the DMA channel
transfers from the UART module to DMA RAM. Figure 10-1 illustrates the organization of the 16-bit
word transferred by DMA from the UART module to the DMA RAM.
Figure 10-1: Format of 16-Bit UART Receive Data Word Transferred by DMA to RAM
The UARTx Error Interrupt Flag bit (UxEIF) gets set if the last UART reception caused a framing
or a parity error. Setting the UxEIE bit causes the CPU to enter the UART error Interrupt Service
Routine (ISR). The user application can then inspect the upper byte of the last transferred word
to check which error condition has caused the interrupt.

12 10 9 bit 0711bit 15 8
Received UART ByteFERR PERR

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