# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Reset

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© 2011 Microchip Technology Inc. DS39712D-page 7-19
Section 7. Reset
Reset
7
The Reset time line displayed in Figure 7-8 provides an example of where the FRC or LPRC sys-
tem clock source is selected. This sequence also applies if an external clock source is used with
two-speed start-up enabled.
Figure 7-8: Device Reset Delay, FRC or LPRC Clocks
7.15 SPECIAL FUNCTION REGISTER (SFR) RESET STATES
Most of the Special Function Registers (SFRs) associated with the PIC24F CPU and peripherals
are reset to a particular value at a device Reset. The SFRs are grouped by their peripheral or
CPU function and their Reset values are specified in the corresponding section of this manual.
The Reset value for each SFR does not depend on the type of Reset, with the exception of two
registers. The Reset value for the Reset Control register, RCON, will depend on the type of
device Reset. The Reset value for the Oscillator Control register, OSCCON, will depend on the
type of Reset and the programmed values of the oscillator Configuration bits in the FOSC Device
Configuration register (see Table 7-1).
POR Circuit Threshold Voltage
Internal Power-on Reset Pulse
TPOR
(2)
VDD
Oscillator Released to System
POR
System Reset Released
Note 1: Delay times shown are not drawn to scale.
2: T
POR = Power-on Reset delay.
3: T
STARTUP = TVREG if the on-chip regulator is enabled or TPWRT if it is disabled.
4: T
RST = Internal State Reset time.
5: T
FRC for the FRC oscillator, TLPRC for the internal 31 kHz RC oscillator.
OSC Delay
(1,5)
T STARTUP
(3)
T RST
(4)
SYSRST
(1)
(Note 5)

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