# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 334 © 2005-2011 Microchip Technology Inc.
[Ws++], [Wd++]
[Ws--], [Wd--]
[++Ws], [++Wd]
[--Ws], [--Wd]
Operands: Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]
Operation: (Ws)
+ 1 → Wd
Status Affected: DC, N, OV, Z, C
Encoding: 1110 1010 0Bqq qddd dppp ssss
Description: Compute the two’s complement of the contents of the source register Ws
and place the result in the destination register Wd. Either register direct
or indirect addressing may be used for both Ws and Wd.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
Words: 1
Cycles:
1
(1)
Note 1:
In dsPIC33E and PIC24E devices, the listed cycle count does not apply to read and
read-modify-write operations on non-CPU Special Function Registers. For more
details, see
Note 3
in
Section 3.2.1 “Multi-Cycle Instructions”
.
Example 1:
NEG.B W3, [W4++] ; Negate W3 and store to [W4] (Byte mode)
; Post-increment W4
Before
Instruction
After
Instruction
W3 7839 W3 7839
W4 1005 W4 1006
Data 1004 2355 Data 1004 C755
SR 0000 SR 0008 (N = 1)
NEG
Negate Ws
Example 2:
NEG [W2++], [--W4] ; Pre-decrement W4 (Word mode)
; Negate [W2] and store to [W4]
; Post-increment W2
Before
Instruction
After
Instruction
W2 0900 W2 0902
W4 1002 W4 1000
Data 0900 870F Data 0900 870F
Data 1000 5105 Data 1000 78F1
SR 0000 SR 0000

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