# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Interrupts

- 1
- 2
…
- 11
- 12
- 13
- 14
- 15
…
- 25
- 26

© 2006 Microchip Technology Inc. Advance Information DS39707A-page 8-13
Section 8. Interrupts
Interrupts
8
Register 8-1: SR: CPU STATUS Register
Register 8-2: CORCON: Core Control Register
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — DC
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
IPL2
(1,2)
IPL1
(1,2)
IPL0
(1,2)
RA N OV Z C
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at any Reset ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 IPL2:IPL0: CPU Interrupt Priority Level Status bits
(1,2)
111 = CPU interrupt priority level is 7 (15). User interrupts disabled.
110 = CPU interrupt priority level is 6 (14)
101 = CPU interrupt priority level is 5 (13)
100 = CPU interrupt priority level is 4 (12)
011 = CPU interrupt priority level is 3 (11)
010 = CPU interrupt priority level is 2 (10)
001 = CPU interrupt priority level is 1 (9)
000 = CPU interrupt priority level is 0 (8)
Note 1: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU interrupt priority
level. The value in parentheses indicates the IPL if IPL<3> = 1.
2: The IPL<2:0> status bits are read-only when NSTDIS = 1 (INTCON1<15>).
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R/C-0 R/W-0 U-0 U-0
— — — — IPL3
(1)
PSV — —
bit 7 bit 0
Legend: C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at any Reset ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 3 IPL3: CPU Interrupt Priority Level Status bit 3
(1)
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.

- 1
- 2
…
- 11
- 12
- 13
- 14
- 15
…
- 25
- 26