# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 -- UART

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dsPIC33/PIC24 Family Reference Manual
DS70000582E-page 8  2009-2013 Microchip Technology Inc.
bit 7-6 URXISEL<1:0>: UARTx Receive Interrupt Mode Selection bits
11 = Interrupt flag bit is set when the receive buffer is full (i.e., 4 data characters)
10 = Interrupt flag bit is set when the receive buffer is 3/4 full (i.e., 3 data characters)
0x = Interrupt flag bit is set when a character is received
bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode is enabled; if 9-bit mode is not selected, this control bit has no effect
0 = Address Detect mode is disabled
bit 4 RIDLE: Receiver Idle bit (read-only)
1 = Receiver is Idle
0 = Data is being received
bit 3 PERR: Parity Error Status bit (read-only)
1 = Parity error has been detected for the current character
0 = Parity error has not been detected
bit 2 FERR: Framing Error Status bit (read-only)
1 = Framing error has been detected for the current character
0 = Framing error has not been detected
bit 1 OERR: Receive Buffer Overrun Error Status bit (clear/read-only)
1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed (clearing a previously set OERR bit will reset the receive buffer
and RSR to an empty state)
bit 0 URXDA: UARTx Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data; at least one more character can be read
0 = Receive buffer is empty
Register 2-2: UxSTA: UARTx Status and Control Register (Continued)
Note 1: This bit is only available in devices supporting Smart Card. Refer to the “Universal Asynchronous
Receiver Transmitter (UART)” chapter of the specific device data sheet for availability.
2: Enable the UARTEN bit (UxMODE<15>) before enabling this bit.
3: User software should wait at least one instruction cycle between writing UxTXREG and reading the TRMT bit.

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