# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004

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PIC24FJ64GA004 FAMILY
DS39881E-page 2  2010-2013 Microchip Technology Inc.
Pin Diagrams
PIC24FJXXGA002
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28-Pin SPDIP, SSOP, SOIC
28-Pin QFN
(1)
10 11
2
3
6
1
18
19
20
21
22
12 13 14
15
8
7
16
17
232425262728
9
PIC24FJXXGA002
5
4
MCLR
VSS
VDD
AN0/VREF+/CN2/RA0
AN1/V
REF-/CN3/RA1
PGED1/AN2/C2IN-/RP0/CN4/RB0
SOSCO/T1CK/CN0/PMA1/RA4
SOSCI/RP4/PMBE/CN1/RB4
OSCO/CLKO/CN29/PMA0/RA3
OSCI/CLKI/CN30/RA2
AN5/C1IN+/SCL2/RP3/CN7/RB3
AN4/C1IN-/SDA2/RP2/CN6/RB2
PGEC1/AN3/C2IN+/RP1/CN5/RB1
PGED3/ASDA1/RP5/CN27/PMD7/RB5
V
DD
VSS
PGEC3/ASCL1/RP6/CN24/PMD6/RB6
DISVREG
V
CAP/VDDCORE
RP7/INT0/CN23/PMD5/RB7
TDO/SDA1/RP9/CN21/PMD3/RB9
TCK/SCL1/RP8/CN22/PMD4/RB8
AN9/RP15/CN11/PMCS1/RB15
AN10/CV
REF/RTCC/RP14/CN12/PMWR/RB14
AN11/RP13/CN13/PMRD/RB13
AN12/RP12/CN14/PMD0/RB12
PGED2/TDI/RP10/CN16/PMD2/RB10
PGEC2/TMS/RP11/CN15/PMD1/RB11
V
SS
PGED1/AN2/C2IN-/RP0/CN4/RB0
OSCO/CLKO/CN29/PMA0/RA3
OSCI/CLKI/CN30/RA2
AN5/C1IN+/SCL2/RP3/CN7/RB3
AN4/C1IN-/SDA2/RP2/CN6/RB2
PGEC1/AN3/C2IN+/RP1/CN5/RB1
DISVREG
V
CAP/VDDCORE
TDO/SDA1/RP9/CN21/PMD3/RB9
AN11/RP13/CN13/PMRD/RB13
AN12/RP12/CN14/PMD0/RB12
PGED2/TDI/RP10/CN16/PMD2/RB10
PGEC2/TMS/RP11/CN15/PMD1/RB11
VDD
PGEC3/ASCL1/RP6/CN24/PMD6/RB6
SOSCO/T1CK/CN0/PMA1/RA4
SOSCI/RP4/PMBE/CN1/RB4
RP7/INT0/CN23/PMD5/RB7
TCK/SCL1/RP8/CN22/PMD4/RB8
PGED3/ASDA1/RP5/CN27/PMD7/RB5
MCLR
AN0/VREF+/CN2/RA0
AN1/V
REF-/CN3/RA1
V
DD
VSS
AN9/RP15/CN11/PMCS1/RB15
AN10/CV
REF/RTCC/RP14/CN12/PMWR/RB14
Legend: RPn represents remappable peripheral pins. Gray shading indicates 5.5V tolerant input pins.
Note 1: Back pad on QFN devices should be connected to Vss.

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