# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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 2007-2014 Microchip Technology Inc. DS70000195F-page 53
Figure 7-12: Slave Message (Write Data to Slave: 10-Bit Address; Address Matches; A10M = 1; GCEN = 0; IPMIEN = 0; AHEN =
STRICT = 0 and BOEN = 0)
1
Slave recognizes Start event, S and P bits set/clear accordingly.
SCLx (Master)
SDAx (Master)
SCLx (Slave)
SDAx (Slave)
I2CxRCV
RBF
SI2CxIF
STREN
1 2 3 4 5 6 7 8
A9A8
9
A
A7A6 A5A4 A3A2 A1
1 2 3 4 5 6 7 8 9
1 32
A
4 4
2 Slave receives address byte. High-order address matches.
3 Slave receives address byte. Low-order address matches.
4 Next received byte is message data. Byte moved to the I2CxRCV
5
User software reads I2CxRCV register. RBF bit clears.
6
Slave recognizes Stop event, S and P bits set/clear accordingly
Slave Acknowledges and generates interrupt. Address byte is
Slave Acknowledges and generates interrupt.
S
P
I2COV
R/W
D/A
D7D6D5D4D3D2D1
1 2 3 4 5 6 7 8 9
A
D7D6D5D4D3D2D1
1 2 3 4 5 6 7 8 9
A
D7D6D5D4D3
1 2 3 4 5
SCLREL
5 5
1 1 1 1 0
Slave Acknowledges and generates interrupt. Address byte is
moved to the I2CxRCV register and is read by user software to prevent
moved to the I2CxRCV register and is read by user software to prevent
buffer overflow.
buffer overflow.
W
A0 D0 D0
SI2CxIF Cleared by User Software

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