# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Motor Control PWM

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PIC24F Family Reference Manual
DS39735A-page 47-8 Preliminary © 2010 Microchip Technology Inc.
Register 47-5: PWMxCON1: PWM Control Register 1
(1)
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
     PMOD3 PMOD2 PMOD1
bit 15 bit 8
U-0 R/W-x
(2)
R/W-x
(2)
R/W-x
(2)
U-0 R/W-x
(2)
R/W-x
(2)
R/W-x
(2)
 PEN3H PEN2H PEN1H  PEN3L PEN2L PEN1L
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as 0
bit 10 PMOD3: PWM I/O Pair 3 Mode bit
1 = PWM I/O pin pair is in the Independent Output mode
0 = PWM I/O pin pair is in the Complementary Output mode
bit 9 PMOD2: PWM I/O Pair 2 Mode bit
1 = PWM I/O pin pair is in the Independent Output mode
0 = PWM I/O pin pair is in the Complementary Output mode
bit 8 PMOD1: PWM I/O Pair 1 Mode bit
1 = PWM I/O pin pair is in the Independent Output mode
0 = PWM I/O pin pair is in the Complementary Output mode
bit 7 Unimplemented: Read as 0
bit 6 PEN3H: PWMxH3 I/O Enable bit
(2)
1 = PWMxH3 pin is enabled for PWM output
0 = PWMxH3 pin is disabled; I/O pin becomes general purpose I/O
bit 5 PEN2H: PWMxH2 I/O Enable bit
(2)
1 = PWMxH2 pin is enabled for PWM output
0 = PWMxH2 pin is disabled; I/O pin becomes general purpose I/O
bit 4 PEN1H: PWMxH1 I/O Enable bit
(2)
1 = PWMxH1 pin is enabled for PWM output
0 = PWMxH1 pin is disabled; I/O pin becomes general purpose I/O
bit 3 Unimplemented: Read as 0
bit 2 PEN3L: PWMxL3 I/O Enable bit
(2)
1 = PWMxL3 pin is enabled for PWM output
0 = PWMxL3 pin is disabled; I/O pin becomes general purpose I/O
bit 1 PEN2L: PWMxL2 I/O Enable bit
(2)
1 = PWMxL2 pin is enabled for PWM output
0 = PWMxL2 pin is disabled; I/O pin becomes general purpose I/O
bit 0 PEN1L: PWMxL1 I/O Enable bit
(2)
1 = PWMxL1 pin is enabled for PWM output
0 = PWMxL1 pin is disabled; I/O pin becomes general purpose I/O
Note 1: In devices where the PWMLOCK bit is present in the FOSCSEL Configuration register, this register can be
write-protected. If the PWMLOCK input signal is asserted (PWMLOCK = 1), the PWMxCON1 register is
writable only after the proper sequence is written to the PWMKEY register. If the PWMLOCK input signal is
deasserted (PWMLOCK = 0), the PWMxCON1 register is writable at all times. Refer to Section 47.14.4
Write-Protected Registers for further details about the unlock sequence.
2: The Reset condition of the PEN3H:PEN1H and PEN3L:PEN1L bits depend on the value of the PWMPIN
device Configuration bit in the FPOR Configuration register. When PWMPIN is set to 0, Reset values are
1 and when PWMPIN is set to 1, Reset values are 0.

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