# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 126 © 2005-2011 Microchip Technology Inc.
BRA
Branch Unconditionally
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} BRA Expr
Operands:
Expr may be a label, absolute address or expression.
Expr is resolved by the linker to a Slit16, where Slit16 ∈ [-32768 ... +32767].
Operation:
(PC + 2) + 2 * Slit16 → PC
NOP → Instruction Register
Status Affected:
None
Encoding: 0011 0111 nnnn nnnn nnnn nnnn
Description: The program will branch unconditionally, relative to the next PC. The offset
of the branch is the two’s complement number ‘2 * Slit16’, which supports
branches up to 32K instructions forward or backward. The Slit16 value is
resolved by the linker from the supplied label, absolute address or
expression. After the branch is taken, the new address will be (PC + 2) + 2 *
Slit16, since the PC will have incremented to fetch the next instruction.
The ‘n’ bits are a signed literal that specifies the number of program words
offset from (PC + 2).
Words:
1
Cycles:
2 (PIC24F, PIC24H, dsPIC30F, dsPIC33F)
4 (PIC24E, dsPIC33E)
Example 1:
002000 HERE: BRA THERE
002002 . . .
002004 . . .
002006 . . .
002008 . . .
00200A THERE: . . .
00200C . . .
; Branch to THERE
Before
Instruction
After
Instruction
PC 00 2000 PC 00 200A
SR 0000 SR 0000
Example 2:
002000 HERE: BRA THERE+0x2
002002 . . .
002004 . . .
002006 . . .
002008 . . .
00200A THERE: . . .
00200C . . .
; Branch to THERE+0x2
Before
Instruction
After
Instruction
PC 00 2000 PC 00 200C
SR 0000 SR 0000

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