# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Family Data Sheet

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DS39997C-page 40 Preliminary © 2011-2012 Microchip Technology Inc.
TABLE 4-6: TIMERS REGISTER MAP FOR PIC24FJ16MC101/102 DEVICES
SFR
Name
SFR
Addr
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
TMR1 0100 Timer1 Register
PR1 0102 Period Register 1
T1CON 0104 TON
— TSIDL — — — — — — TGATE TCKPS<1:0> — T
TMR2 0106 Timer2 Register
TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only)
TMR3 010A Timer3 Register
PR2 010C Period Register 2
PR3 010E Period Register 3
T2CON 0110 TON
— TSIDL — — — — — — TGATE TCKPS<1:0> T32
T3CON 0112 TON
— TSIDL — — — — — — TGATE TCKPS<1:0> —
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-7: TIMERS REGISTER MAP FOR PIC24FJ32MC101/102/104 DEVICES
SFR
Name
SFR
Addr
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
TMR1 0100 Timer1 Register
PR1 0102 Period Register 1
T1CON 0104 TON
— TSIDL — — — — — — TGATE TCKPS<1:0> — T
TMR2 0106 Timer2 Register
TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only)
TMR3 010A Timer3 Register
PR2 010C Period Register 2
PR3 010E Period Register 3
T2CON 0110 TON
— TSIDL — — — — — — TGATE TCKPS<1:0> T32
T3CON 0112 TON
— TSIDL — — — — — — TGATE TCKPS<1:0> —
TMR4 0114 Timer4 Register
TMR5HLD 0116 Timer5 Holding Register (for 32-bit operations only)
TMR5 0118 Timer5 Register
PR4 011A Period Register 4
PR5 011C Period Register 5
T4CON 011E TON
— TSIDL — — — — — — TGATE TCKPS<1:0> T32
T5CON 0120 TON
— TSIDL — — — — — — TGATE TCKPS<1:0> —
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

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