# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 32 © 2005-2011 Microchip Technology Inc.
Register 2-5: CORCON: Core Control Register (PIC24E Devices)
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
VAR — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R/C-0 R-0 U-0 U-0
— — — — IPL3
(1,2)
SFA — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 VAR: Variable Exception Processing Latency Control bit
1 = Variable (bounded deterministic) exception processing latency
0 = Fixed (fully deterministic) exception processing latency
bit 14-4 Unimplemented: Read as '0’
bit 3 IPL3: CPU Interrupt Priority Level Status bit 3
(1)
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
bit 2 SFA: Stack Frame Active Status bit
1 = Stack frame is active. W14 and W15 address 0x0000 to 0xFFFF, regardless of DSRPAG and
DSWPAG values.
0 = Stack frame is not active. W14 and W15 address of EDS or Base Data Space
bit 1-0 Unimplemented: Read as '0’
Note 1: This bit may be read or cleared, but not set.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.

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