# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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dsPIC33/PIC24 Family Reference Manual
DS70000195F-page 62  2007-2014 Microchip Technology Inc.
Figure 8-1: Sample Device Configuration for I
2
C™ Bus
8.1 Integrated Signal Conditioning
The SCLx and SDAx pins have an input glitch filter. The I
2
C bus requires this filter in both the
100 kHz and 400 kHz systems.
When operating on a 400 kHz bus, the I
2
C bus specification requires a slew rate control of the
device pin output. This slew rate control is integrated into the device. If the DISSLW bit
(I2CxCON<9> or I2CxCONL<9>) is cleared, the slew rate control is active. For other bus speeds,
the I
2
C bus specification does not require slew rate control and the DISSLW bit should be set.
Some system implementations of I
2
C buses require different input levels for VILMAX and V IHMIN.
In a normal I
2
C system, VILMAX is 0.3 V DD; VIHMIN is 0.7 VDD. By contrast, in a SMBus system,
V
ILMAX is set at 0.8V, while VIHMIN is set at 2.1V.
The SMEN bit (I2CxCON<8> or I2CxCONL<8>) controls the input levels. Setting SMEN (= 1)
changes the input levels to SMBus specifications.
RP RP
VDD + 10%
SDAx
SCLx
CB = 10-400 pF
R
S RS
Note: I
2
C™ devices with input levels related to VDD must have one common supply
line to which the pull-up resistor is also connected.
Device

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