# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Oscillator

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PIC24F Family Reference Manual
DS39700C-page 6-30 © 2009 Microchip Technology Inc.
6.13 REFERENCE CLOCK OUTPUT GENERATOR
The CLKO output available on OSC2 in select oscillator modes can be useful for synchronizing
external logic to the microcontroller. However, it is limited in that it is only available in a few
modes, and at only one frequency (FOSC/2). For select PIC24F families, the reference clock
output generator provides another option: a separate synchronous and programmable clock
source to the REFO port pin.
The reference clock output generator receives inputs from both the Primary Oscillator and the
currently selected system clock. This allows the user to select an output clock signal with a
constant frequency, or an output clock that changes as the system clock changes during run time
(e.g., on a change to or from a lower power mode). A 16-step divider allows for the selection of
a wide range of system clock submultiples. Reference clock changes due to system clock
frequency changes occur in a glitchless fashion.
This reference clock output is controlled by the REFOCON register (Register 6-4). Setting the ROEN
bit (REFOCON<15>) makes the clock signal available on the REFO pin. The RODIV bits
(REFOCON<11:8>) select a range of output frequencies, from divide-by-1 through
divide-by-32,768. This postscaler can be changed as needed at run time. It is recommended that the
clock generator be disabled prior to changing the RODIV bits to ensure the smoothest speed
transition.
The ROSEL bit (REFOCON<12>) determines if the Primary Oscillator, or the current system
clock source designated by COSC<2:0>, provides the reference clock output. Clearing the
ROSEL bit allows the reference output frequency to change as the system clock changes during
any clock switches.
If one of the Primary Oscillator modes (EC, HS or XT) is used for the system clock, the ROSEL
and ROSSLP bits determine if the reference clock output is available when the device is in Sleep
mode. Both the ROSSLP and ROSEL bits must be set, and the POSCEN bit (OSCCON<2>)
must also be set. Otherwise, the oscillator on OSC1 and OSC2 will be powered down when the
device enters Sleep mode.

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