# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 94 © 2005-2011 Microchip Technology Inc.
5.1 INSTRUCTION SYMBOLS
All the symbols used in Section 5.4 “Instruction Descriptions” are listed in Table 1-2.
5.2 INSTRUCTION ENCODING FIELD DESCRIPTORS INTRODUCTION
All instruction encoding field descriptors used in Section 5.4 “Instruction Descriptions” are
shown in Table 5-2 through Table 5-12.
Table 5-1: Instruction Encoding Field Descriptors
Field Description
A
(1)
Accumulator selection bit: 0 = ACCA; 1 = CCB
aa
(1)
Accumulator Write Back mode (see Table 5-12)
B Byte mode selection bit: 0 = word operation; 1 = byte operation
bbbb 4-bit bit position select: 0000 = LSB; 1111 = MSB
D Destination address bit: 0 = result stored in WREG;
1 = result stored in file register
dddd Wd destination register select: 0000 = W0; 1111 = W15
f ffff ffff ffff 13-bit register file address (0x0000 to 0x1FFF)
fff ffff ffff ffff 15-bit register file word address (implied 0 LSB)
(0x0000 to 0xFFFE)
ffff ffff ffff ffff 16-bit register file byte address (0x0000 to 0xFFFF)
ggg Register Offset Addressing mode for Ws source register (see
Table 5-4)
hhh Register Offset Addressing mode for Wd destination register (see Table 5-5)
iiii
(1)
Prefetch X Operation (see Table 5-6)
jjjj
(1)
Prefetch Y Operation (see Table 5-8)
k 1-bit literal field, constant data or expression
kkkk 4-bit literal field, constant data or expression
kk kkkk 6-bit literal field, constant data or expression
kkkk kkkk 8-bit literal field, constant data or expression
kk kkkk kkkk 10-bit literal field, constant data or expression
kk kkkk kkkk kkkk 14-bit literal field, constant data or expression
kkkk kkkk kkkk kkkk 16-bit literal field, constant data or expression
mm Multiplier source select with same working registers (see
Table 5-10)
mmm Multiplier source select with different working registers (see Table 5-11)
nnnn nnnn nnnn nnn0
nnn nnnn
23-bit program address for CALL and GOTO instructions
nnnn nnnn nnnn nnnn 16-bit program offset field for relative branch/call instructions
ppp Addressing mode for Ws source register (see Table 5-2)
qqq Addressing mode for Wd destination register (see Table 5-3)
rrrr Barrel shift count
ssss Ws source register select: 0000 = W0; 1111 = W15
tttt Dividend select, most significant word
vvvv Dividend select, least significant word
W Double Word mode selection bit: 0 = word operation;
1 = double word operation
wwww Wb base register select: 0000 = W0; 1111 = W15
xx
(1)
Prefetch X Destination (see Table 5-7)
xxxx xxxx xxxx xxxx 16-bit unused field (don’t care)
yy
(1)
Prefetch Y Destination (see Table 5-9)
z Bit test destination: 0 = C flag bit; 1 = Z flag bit
Note 1: This field is only available in dsPIC30F, dsPIC33F, and dsPIC33E devices.

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