# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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© 2005-2011 Microchip Technology Inc. DS70157F-page 255
Section 5. Instruction Descriptions
Instruction
Descriptions
5
INC
Increment Ws
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} INC{.B} Ws, Wd
[Ws], [Wd]
[Ws++], [Wd++]
[Ws--], [Wd--]
[++Ws], [++Wd]
[--Ws], [--Wd]
Operands: Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]
Operation: (Ws) + 1 → Wd
Status Affected: DC, N, OV, Z, C
Encoding:
1110 1000 0Bqq qddd dppp ssss
Description: Add 1 to the contents of the source register Ws and place the result in the
destination register Wd. Register direct or indirect addressing may be
used for Ws and Wd.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
Words: 1
Cycles:
1
(1)
Note 1:
In dsPIC33E and PIC24E devices, the listed cycle count does not apply to read and
read-modify-write operations on non-CPU Special Function Registers. For more
details, see
Note 3
in
Section 3.2.1 “Multi-Cycle Instructions”
.
Example 1:
INC.B W1, [++W2] ; Pre-increment W2
; Increment W1 and store to W2
; (Byte mode)
Before
Instruction
After
Instruction
W1 FF7F W1 FF7F
W2 2000 W2 2001
Data 2000 ABCD Data 2000 80CD
SR 0000 SR 010C (DC, N, OV = 1)

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