# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Oscillator

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© 2009 Microchip Technology Inc. DS39700C-page 6-17
Section 6. Oscillator
Oscillator
6
A method for improving start-up is to use a value of C2 greater than C1. This causes a greater phase
shift across the crystal at power-up, which speeds oscillator start-up. Besides loading the crystal for
proper frequency response, these capacitors can have the effect of lowering loop gain if their value
is increased. C2 can be selected to affect the overall gain of the circuit. A higher C2 can lower the
gain if the crystal is being overdriven (also, see discussion on Rs). Capacitance values that are too
high can store and dump too much current through the crystal, so C1 and C2 should not become
excessively large. Unfortunately, measuring the wattage through a crystal is difficult, but if you do not
stray too far from the suggested values, you should not have to be concerned with this.
A series resistor, Rs, is added to the circuit if, after all other external components are selected to
satisfaction, the crystal is still being overdriven. This can be determined by looking at the OSC2
pin, which is the driven pin, with an oscilloscope. Connecting the probe to the OSC1 pin will load
the pin too much and negatively affect performance. Remember that a scope probe adds its own
capacitance to the circuit, so this may have to be accounted for in your design (i.e., if the circuit
worked best with a C2 of 22 pF and the scope probe was 10 pF, a 33 pF capacitor may actually
be called for). The output signal should not be clipping or flattened. Overdriving the crystal can
also lead to the circuit jumping to a higher harmonic level, or even, crystal damage.
The OSC2 signal should be a clean sine wave that easily spans the input minimum and maximum
of the clock input pin. An easy way to set this is to again test the circuit at the minimum temper-
ature and maximum V
DD that the design will be expected to perform in, then look at the output.
This should be the maximum amplitude of the clock output. If there is clipping, or the sine wave
is distorted near VDD and VSS, increasing load capacitors may cause too much current to flow
through the crystal or push the value too far from the manufacturer’s load specification. To adjust
the crystal current, add a trimmer potentiometer between the crystal inverter output pin and C2,
and adjust it until the sine wave is clean. The crystal will experience the highest drive currents at
the low temperature and high V
DD extremes.
The trimmer potentiometer should be adjusted at these limits to prevent overdriving. A series
resistor, Rs, of the closest standard value can now be inserted in place of the trimmer. If Rs is
too high, perhaps more than 20 kΩ, the input will be too isolated from the output, making the clock
more susceptible to noise. If you find a value this high is needed to prevent overdriving the
crystal, try increasing C2 to compensate or changing the oscillator operating mode. Try to get a
combination where Rs is around 10 kΩ, or less, and load capacitance is not too far from the
manufacturer’s specification.
6.5.3 External Clock Input
In EC mode, the OSC1 pin is in a high-impedance state and can be driven by CMOS drivers. The
OSC2 pin can be configured as either an I/O or the clock output (F
OSC/2) by selecting the
OSCIOFCN bit (Configuration Word 2<5>). With OSCIOFCN set (Figure 6-5), the clock output is
available for testing or synchronization purposes. With OSCIOFCN clear (Figure 6-6), the OSC2
pin becomes a general purpose I/O pin. The feedback device between OSC1 and OSC2 is
turned off to save current.
Figure 6-5: External Clock Input Operation (OSCIOFCN = 1)
Figure 6-6: External Clock Input Operation (OSCIOFCN = 0)
OSC1
OSC2F
OSC/2
Clock from
External System
PIC24F
OSC1
I/O (OSC2)I/O
Clock from
External System
PIC24F

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