# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- CPU

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PIC24F Family Reference Manual
DS39703A-page 2-14 Advance Information © 2006 Microchip Technology Inc.
2.6 MULTIPLICATION AND DIVIDE SUPPORT
2.6.1 Overview
The PIC24F core contains a 17-bit x 17-bit multiplier and is capable of unsigned, signed or mixed
sign operation with the following multiplication modes:
1. 16-Bit x 16-Bit Signed
2. 16-Bit x 16-Bit Unsigned
3. 16-Bit Signed x 5-Bit (literal) Unsigned
4. 16-Bit Unsigned x 16-Bit Unsigned
5. 16-Bit Unsigned x 5-Bit (literal) Unsigned
6. 16-Bit Unsigned x 16-Bit Signed
7. 8-Bit Unsigned x 8-Bit Unsigned
The divide block is capable of supporting 32-bit/16-bit and 16-bit/16-bit signed and unsigned
integer divide operation with the following data sizes:
1. 32-bit signed/16-bit signed divide
2. 32-bit unsigned/16-bit unsigned divide
3. 16-bit signed/16-bit signed divide
4. 16-bit unsigned/16-bit unsigned divide
2.6.2 Multiplier
A block diagram of the multiplier is shown in Figure 2-8. It is used to support the multiply instructions
which include integer 16-bit signed, unsigned and mixed sign multiplies, including the PIC18F
unsigned multiply, MULWF (MUL.w and MUL.b). All multiply instructions only support Register Direct
Addressing mode for the result. A 32-bit result (from all multiplies other than MULWF) is written to
any two aligned consecutive W register pairs, except W15:W14, which are not allowed.
The MULWF instruction may be directed to use byte or word sized operands. The destination is
always the W3:W2 register pair in the W array. Byte multiplicands will direct a 16-bit result to W2
(W3 is not changed), and word multiplicands will direct a 32-bit result to W3:W2.
The multiplicands for all multiply instructions (other than MULWF which is a special case) are
derived from the W array (1st word) and data space (2nd word). MULWF derives its multiplicands
from W2 (1st word or byte) and data space (2nd word or byte) using a zero-extended, 13-bit
absolute address.
Additional data paths are provided to allow these instructions to write the result back into the W
array and data bus (via the W array) as shown in Figure 2-8.
Note: The destination register pair for multiply instructions must be ‘aligned’ (i.e.,
odd:even), where ‘odd’ contains the most significant result word and ‘even’ contains
the least significant result word. For example, W3:W2 is acceptable, whereas
W4:W3 is not.

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