# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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 2007-2014 Microchip Technology Inc. DS70000195F-page 9
Inter-Integrated Circuit™ (I
2
C™)
Register 3-1: I2CxCON: I2Cx Control Register
R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0
I2CEN
— I2CSIDL SCLREL IPMIEN
(1)
A10M DISSLW SMEN
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC
GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0
Legend: HC = Hardware Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at Reset ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 I2CEN: I2Cx Enable bit
1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins
0 = Disables the I2Cx module; all the I
2
C™ pins are controlled by port functions
bit 14 Unimplemented: Read as ‘0’
bit 13 I2CSIDL: I2Cx Stop in Idle Mode bit
1 = Discontinues the module operation when a device enters the Idle mode
0 = Continues the module operation in the Idle mode
bit 12 SCLREL: SCLx Release Control bit (when operating as I
2
C slave)
1 = Releases the SCLx clock
0 = Holds SCLx clock low (clock stretch)
If STREN =
1:
User software may write ‘0’ to initiate a clock stretch and write ‘1’ to release the clock. Hardware clears
at the beginning of every slave data byte transmission. Hardware clears at the end of every slave
address byte reception. Hardware clears at the end of every slave data byte reception.
If STREN =
0:
User software may only write ‘1’ to release the clock. Hardware clears at the beginning of every slave
data byte transmission. Hardware clears at the end of every slave address byte reception.
bit 11 IPMIEN: IPMI Enable bit
(1)
1 = IPMI Support mode is enabled, all addresses are Acknowledged
0 = IPMI Support mode is disabled
bit 10 A10M: 10-Bit Slave Address bit
1 = I2CxADD register is a 10-bit slave address
0 = I2CxADD register is a 7-bit slave address
bit 9 DISSLW: Disable Slew Rate Control bit
1 = Slew rate control is disabled
0 = Slew rate control is enabled
bit 8 SMEN: SMBus Input Levels bit
1 = Enables the I/O pin thresholds compliant with the SMBus specification
0 = Disables the SMBus input thresholds
bit 7 GCEN: General Call Enable bit (when operating as I
2
C slave)
1 = Enables the interrupt when a general call address is received in the I2CxRSR register (module is
enabled for reception)
0 = Disables the general call address
bit 6 STREN: SCLx Clock Stretch Enable bit (I
2
C Slave mode only; used in conjunction with the SCLREL bit)
1 = Enables the user software or the receive clock stretching
0 = Disables the user software or the receive clock stretching
Note 1: The IPMIEN bit should not be set when the I
2
C module is operating as a master.

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