# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- 10-Bit ADC

- 1
- 2
…
- 5
- 6
- 7
- 8
- 9
…
- 57
- 58

© 2010 Microchip Technology Inc. Preliminary DS39737A-page 49-7
Section 49. 10-Bit ADC with 4 Simultaneous Conversions
10-Bit ADC with
4 Simultaneous
Conversions
49
Register 49-3: ADxCON3: ADCx Control Register 3
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADRC
— — SAMC4
(1,2)
SAMC3
(1,2)
SAMC2
(1,2)
SAMC1
(1,2)
SAMC0
(1,2)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ADRC: ADC Conversion Clock Source bit
1 = ADC internal RC clock
0 = Clock derived from system clock
bit 14-13 Unimplemented: Read as ‘0’
bit 12-8 SAMC<4:0>: Auto-Sample Time bits
(1,2)
11111 = 31 T AD
•
•
•
00001 = 1 T
AD
00000 = 0 T AD
bit 7-0 ADCS<7:0>: ADC Conversion Clock Select bits
11111111 = Reserved
•
•
•
01000000 = Reserved
00111111 = T
CY • (ADCS<7:0> + 1) = 64 • T CY = T AD
•
•
•
00000010 = T
CY • (ADCS<7:0> + 1) = 3 • T CY = T AD
00000001 = T
CY • (ADCS<7:0> + 1) = 2 • T CY = T AD
00000000 = T CY • (ADCS<7:0> + 1) = 1 • T CY = T AD
Note 1: This bit is only used when the SSRC<2:0> bits (ADxCON1<7:5>) = 111.
2: If SSRC<2:0> = 111, the SAMC bit should be set to at least ‘1’ when using one S&H channel or using
simultaneous sampling. When using multiple S&H channels with sequential sampling, the SAMC bit
should be set to ‘0’ for the fastest possible conversion rate.

- 1
- 2
…
- 5
- 6
- 7
- 8
- 9
…
- 57
- 58