# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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 2007-2014 Microchip Technology Inc. DS70000195F-page 5
Inter-Integrated Circuit™ (I
2
C™)
2.1 Bus Protocol
The following I
2
C bus protocol has been defined:
• The data transfer may be initiated only when the bus is not busy.
• During the data transfer, the data line must remain stable whenever the SCLx clock line is
high. Any changes in the data line, while the SCLx clock line is high, will be interpreted as a
Start or Stop condition.
Accordingly, the bus conditions are defined as illustrated in Figure 2-2.
Figure 2-2: I
2
C™ Bus Protocol States
2.1.1 START DATA TRANSFER (S)
After a bus Idle state, a high-to-low transition of the SDAx line while the clock (SCLx) is high
determines a Start condition. All data transfers must be preceded by a Start condition.
2.1.2 STOP DATA TRANSFER (P)
A low-to-high transition of the SDAx line while the clock (SCLx) is high determines a Stop
condition. All data transfers must end with a Stop condition.
2.1.3 REPEATED START (R)
After a Wait state, a high-to-low transition of the SDAx line while the clock (SCLx) is high
determines a Repeated Start condition. Repeated Starts allow a master to change bus direction
or address a slave device without relinquishing control of the bus.
2.1.4 DATA VALID (D)
After a Start condition, the state of the SDAx line represents valid data when the SDAx line is
stable for the duration of the high period of the clock signal. There is one bit of data per SCLx
clock.
2.1.5 ACKNOWLEDGE (A) OR NOT ACKNOWLEDGE (N)
All data byte transmissions must be Acknowledged (ACK) or Not Acknowledged (NACK) by the
receiver. The receiver will pull the SDAx line low for an ACK
or release the SDAx line for a NACK.
The Acknowledge is a 1-bit period using one SCLx clock.
2.1.6 WAIT/DATA INVALID (Q)
The data on the line must be changed during the low period of the clock signal. The devices may
also stretch the clock low time by asserting a low on the SCLx line, causing a Wait on the bus.
2.1.7 BUS IDLE (I)
Both data and clock lines remain high after a Stop condition and before a Start condition.
Address
Valid
Data
Allowed
to Change
Stop
Condition
Start
Condition
SCLx
SDAx
(I) (S) (D) (A) or (N) (P) (I)
Data or
(Q)
ACK
/NACK
Valid
NACK
ACK

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