# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 -- Serial Peripheral Interface

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dsPIC33/PIC24 Family Reference Manual
DS70005185A-page 12  2014 Microchip Technology Inc.
3.0 MODES OF OPERATION
The SPIx module consists of the following operating attributes, which are discussed in the
following sections:
• Configuring the Port Pins
• 8-Bit and 16-Bit Data Transmission/Reception
• Master and Slave Modes
• Enhanced Buffer Master and Slave Modes
• Framed SPI Modes
• SPIx Receive Only Operation
• SPIx Error Handling
3.1 Configuring the Port Pins
The SPIx module inputs must be configured as digital pins by setting the corresponding bits in
the ADxPCFG registers, or by clearing the bits in the ANSELx or ANSx registers with respect to
a particular device. If the device has a Peripheral Pin Select (PPS) feature, the SCKx pin must
be mapped as both input and output in Master mode.
3.2 8-Bit and 16-Bit Data Transmission/Reception
The Word/Byte Mode Communication Select bit (MODE16) in SPIx Control Register 1
(SPIxCON1<10>) allows the module to communicate in either 8-bit or 16-bit mode. The
functionality is the same for each mode, except for the number of bits that are received and
transmitted. In this context, read the following:
• The module is reset when the value of the MODE16-bit is changed. Consequently, the bit
must not be changed during normal operation.
• Data is transmitted out of bit 7 of the SPIx Shift register (SPIxSR<7>) for 8-bit operation,
while it is transmitted out of bit 15 (SPIxSR<15>) for 16-bit operation. In both modes, data
is shifted into bit 0 (SPIxSR<0>).
• In 8-bit mode, eight clock pulses are required at the SCKx pin to shift data in and out when
transmitting or receiving data. In 16-bit mode, 16 clock pulses are required at the SCKx pin.
3.3 Master and Slave Modes
Data can be thought of as taking a direct path between the Most Significant bit (MSb) of one
module’s Shift register and the Least Significant bit (LSb) of the other, and then into the
appropriate transmit or receive buffer. A module configured as the master module provides the
serial clock and synchronization signals to the slave device. Figure 3-1 shows the connection
between the master and slave modules.
Note 1: In Framed SPI mode, the SDIx, SDOx, SCKx and SSx
pins are used
2: If the slave select feature is used, then all four pins are used.
3: If the standard SPI mode is used, but CKE = 1, then enabling or using the slave
select feature is mandatory, and therefore, all four pins are used.
4: If the standard SPI mode is used, but DISSDO = 1, then only the SDIx and SCKx
pins (unless slave select is also enabled) are used.
5: In all other cases, the SDIx, SDOx and SCKx pins are used.

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