# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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dsPIC33/PIC24 Family Reference Manual
DS70000195F-page 8  2007-2014 Microchip Technology Inc.
3.0 CONTROL AND STATUS REGISTERS
The I
2
C module has registers for operation that are accessible by the user application. All
registers are accessible in either Byte or Word mode. The registers are as follows:
• I2CxCON: I2Cx Control Register or I2CxCONL: I2Cx Control Register Low and
I2CxCONH: I2Cx Control Register High
These registers allow control of the module’s operation.
• I2CxSTAT: I2Cx Status Register
This register contains status flags indicating the module’s state during operation.
• I2CxMSK: I2Cx Slave Mode Address Mask Register
This register designates which bit positions in the I2CxADD register can be ignored, which
allows for multiple address support.
• ISRCCON: I2Cx Current Source Control Register
(1)
This register allows control of the current source module.
• I2CxRCV: I2Cx Receive Buffer Register
This is the buffer register from which data bytes can be read. The I2CxRCV register is a
read-only register.
• I2CxTRN: I2CxTransmit Register
This is the Transmit register. The bytes are written to this register during a transmit
operation. The I2CxTRN register is a read/write register.
• I2CxADD:I2Cx Address Register
This register holds the slave device address.
• I2CxBRG: I2Cx Baud Rate Generator Reload Register
This register holds the BRG reload value for the I
2
C module BRG.
The transmit data is written to the I2CxTRN register. This register is used when the module
operates as a master transmitting data to the slave or when it operates as a slave sending reply
data to the master. As the message progresses, the I2CxTRN register shifts out the individual
bits. Therefore, the I2CxTRN register cannot be written to unless the bus is Idle.
The data being received by either the master or the slave is shifted into a non-accessible shift
register, I2CxRSR. When a complete byte is received, the byte transfers to the I2CxRCV register.
In receive operations, the I2CxRSR and I2CxRCV registers create a double-buffered receiver.
This allows reception of the next byte to begin before reading the current byte of the received
data.
If the module receives another complete byte before the user software reads the previous byte
from the I2CxRCV register, a receiver overflow occurs and sets the I2COV bit (I2CxSTAT<6>).
The byte in the I2CxRSR register is lost if (BOEN = 0). Further reception and clock stretching
are disabled until the I
2
C module sees a Start/Repeated, Start/Stop condition on the bus. If the
I2COV flag has been cleared, the reception can proceed normally. If the I2COV flag is not
cleared, the module will receive the next byte correctly, but will send a NACK. It will then be
unable to receive further bytes or stretch the clock until it detects a Start/Repeated and Start/Stop
condition.
The I2CxADD register holds the slave device address. In 10-Bit Addressing mode, all bits are
relevant. In 7-Bit Addressing mode, only the I2CxADD<6:0> bits are relevant. The
I2CxADD<6:0> bits correspond to the upper 7 bits in the address byte. The read/write bit is not
included in the value in this register. The A10M bit (I2CxCON<10> or I2CxCONL<10>) specifies
the expected mode of the slave address. By using the I2CxMSK register with the I2CxADD reg-
ister in Slave Addressing mode, one or more bit positions can be removed from the exact
address matching, allowing the module, in Slave mode, to respond to multiple addresses.
Note 1: The I2CxCONL, I2CxCONH and ISRCCON registers are not available on all
devices. Refer to the specific device data sheet for availability.

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