# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# MPLAB XC16 C-Compiler

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MPLAB
®
XC16 C Compiler Users Guide
DS50002071C-page 96  2012-2013 Microchip Technology Inc.
-fgcse-lm When -fgcse-lm is enabled, global common subexpression
elimination will attempt to move loads which are only killed by
stores into themselves. This allows a loop containing a load/store
sequence to be changed to a load outside the loop, and a
copy/store within the loop.
-fgcse-sm When -fgcse-sm is enabled, a store motion pass is run after
global common subexpression elimination. This pass will attempt
to move stores out of loops. When used in conjunction with
-fgcse-lm, loops containing a load/store sequence can be
changed to a load before the loop and a store after the loop.
-fno-defer-pop Always pop the arguments to each function call as soon as that
function returns. The compiler normally lets arguments accumu-
late on the stack for several function calls and pops them all at
once.
-fno-peephole
-fno-peephole2
Disable machine specific peephole optimizations. Peephole opti-
mizations occur at various points during the compilation.
-fno-peephole disables peephole optimization on machine
instructions, while -fno-peephole2 disables high level peep-
hole optimizations. To disable peephole entirely, use both options.
-foptimize-
register-move
-fregmove
Attempt to reassign register numbers in move instructions and as
operands of other simple instructions in order to maximize the
amount of register tying.
-fregmove and -foptimize-register-moves are the same
optimization.
-frename-registers Attempt to avoid false dependencies in scheduled code by mak-
ing use of registers left over after register allocation. This optimi-
zation will most benefit processors with lots of registers. It can,
however, make debugging impossible, since variables will no lon-
ger stay in a home register.
-frerun-cse-after-
loop
Rerun common subexpression elimination after loop
optimizations has been performed.
-frerun-loop-opt Run the loop optimizer twice.
-fschedule-insns Attempt to reorder instructions to eliminate dsPIC® DSC
Read-After-Write stalls (see the dsPIC30F Family Reference
Manual (DS70046) for more details). Typically improves
performance with no impact on code size.
-fschedule-insns2 Similar to -fschedule-insns, but requests an additional pass
of instruction scheduling after register allocation has been done.
-fstrength-reduce Perform the optimizations of loop strength reduction and
elimination of iteration variables.
TABLE 5-12: SPECIFIC OPTIMIZATION OPTIONS (CONTINUED)
Option Definition

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