# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004

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PIC24FJ64GA004 FAMILY
DS39881E-page 116  2010-2013 Microchip Technology Inc.
REGISTER 10-11: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
   SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
   SDI1R4 SDI1R3 SDI1R2 SDI1R1 SDI1R0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as 0
bit 12-8 SCK1R<4:0>: Assign SPI1 Clock Input (SCK1IN) to the Corresponding RPn Pin bits
bit 7-5 Unimplemented: Read as 0
bit 4-0 SDI1R<4:0>: Assign SPI1 Data Input (SDI1) to the Corresponding RPn Pin bits
REGISTER 10-12: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
       
bit 15 bit 8
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
   SS1R4 SS1R3 SS1R2 SS1R1 SS1R0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
bit 15-5 Unimplemented: Read as 0
bit 4-0 SS1R<4:0>: Assign SPI1 Slave Select Input (SS1IN) to the Corresponding RPn Pin bits

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