# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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dsPIC33/PIC24 Family Reference Manual
DS70000195F-page 34  2007-2014 Microchip Technology Inc.
6.0 COMMUNICATING AS A MASTER IN A MULTI-MASTER ENVIRONMENT
The I
2
C protocol allows more than one master to be attached to a system bus. Taking into
account that a master can initiate message transactions and generate clocks for the bus, the
protocol has methods to account for situations where more than one master is attempting to
control the bus. The clock synchronization ensures that multiple nodes can synchronize their
SCLx clocks to result in one common clock on the SCLx line. The bus arbitration ensures that if
more than one node attempts a message transaction, only one node will be successful in
completing the message. The other nodes lose bus arbitration and are left with a bus collision.
6.1 Multi-Master Operation
The master module has no special settings to enable the multi-master operation. The module
performs the clock synchronization and bus arbitration at all times. If the module is used in a
single master environment, clock synchronization only occurs between the master and slaves,
and bus arbitration does not occur.
6.2 Master Clock Synchronization
In a multi-master system, different masters can have different baud rates. The clock
synchronization ensures that when these masters are attempting to arbitrate the bus, their clocks
will be coordinated.
The clock synchronization occurs when the master deasserts the SCLx pin (SCLx intended to
float high). When the SCLx pin is released, the BRG is suspended from counting until the SCLx
pin is actually sampled high. When the SCLx pin is sampled high, the BRG is reloaded with the
contents of I2CxBRG<8:0> and begins counting. This ensures that the SCLx high time will
always be at least one BRG rollover count in the event that the clock is held low by an external
device, as illustrated in Figure 6-1.
Figure 6-1: Baud Rate Generator Timing with Clock Synchronization
Note: The IPMIEN bit (I2CxCON<11>) should not be set when operating as a master.
SCLx (Slave)
The baud counter decrements twice per T CY. On rollover, the master SCLx will transition.
1
1
000 003001002003
SCLx (Master)
001002003000
Baud Counter
SDAx (Master)
3 4 6
The slave has pulled SCLx low to initiate a Wait.
2
At what would be the master baud counter rollover, detecting SCLx low holds counter.
3
Logic samples SCLx once per T
CY. Logic detects SCLx high.
4
2
The baud counter rollover occurs on next cycle.
5
5
On next rollover, the master SCLx will transition.
6
T
BRG TBRG
T CY
000

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