# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Watchdog Timer

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PIC24F Family Reference Manual
DS39697B-page 9-6 © 2010 Microchip Technology Inc.
9.2.5 Resetting the Watchdog Timer
The WDT counter and associated prescalers and postscalers are reset:
• On any device Reset
• When a PWRSAV instruction is executed (i.e., Sleep or Idle mode is entered)
• When the WDT is enabled in software
• On the completion of a clock switch, whether invoked by software (i.e., setting the OSWEN
bit after changing the NOSC bits) or by hardware (i.e., Fail-Safe Clock Monitor)
• By a CLRWDT instruction during normal execution or during the allowed window of the WDT
time-out period if WINDIS is ‘0’ (depending on the WDTWIN setting).
9.2.6 Watchdog Timer Operation in Sleep and Idle Modes
If the WDT is enabled, it will continue to run during Sleep or Idle modes. When the WDT time-out
occurs, it will wake the device and code execution will continue from where the instruction was
executed.
The WDT is useful for low-power system designs, because it can be used to periodically wake
the device from Sleep mode to check system status and provide action if necessary. Note that
the SWDTEN bit is very useful in this respect. If the WDT is disabled during normal operation
(FWDTEN = 0), then the SWDTEN bit (RCON<5>) can be used to turn on the WDT just before
entering Sleep mode.

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