# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004

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 2010-2013 Microchip Technology Inc. DS39881E-page 49
PIC24FJ64GA004 FAMILY
REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER
R/SO-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0
WR WREN WRERR
    
bit 15 bit 8
U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
 ERASE   NVMOP3
(1)
NVMOP2
(1)
NVMOP1
(1)
NVMOP0
(1)
bit 7 bit 0
Legend: SO = Settable Only bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
bit 15 WR: Write Control bit
1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is
cleared by hardware once operation is complete
0 = Program or erase operation is complete and inactive
bit 14 WREN: Write Enable bit
1 = Enables Flash program/erase operations
0 = Inhibits Flash program/erase operations
bit 13 WRERR: Write Sequence Error Flag bit
1 = An improper program or erase sequence attempt or termination has occurred (bit is set
automatically on any set attempt of the WR bit)
0 = The program or erase operation completed normally
bit 12-7 Unimplemented: Read as 0
bit 6 ERASE: Erase/Program Enable bit
1 = Performs the erase operation specified by the NVMOP<3:0> bits on the next WR command
0 = Performs the program operation specified by the NVMOP<3:0> bits on the next WR command
bit 5-4 Unimplemented: Read as 0
bit 3-0 NVMOP<3:0>: NVM Operation Select bits
(1)
1111 = Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)
(2)
0011 = Memory word program operation (ERASE = 0) or no operation (ERASE = 1)
0010 = Memory page erase operation (ERASE = 1) or no operation (ERASE = 0)
0001 = Memory row program operation (ERASE = 0) or no operation (ERASE = 1)
Note 1: All other combinations of NVMOP<3:0> are unimplemented.
2: Available in ICSP mode only. Refer to the device programming specifications.

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