# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 -- Serial Peripheral Interface

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dsPIC33/PIC24 Family Reference Manual
DS70005185A-page 26  2014 Microchip Technology Inc.
3.5 Framed SPI Modes
The SPIx module supports a basic framed SPI protocol while operating in either Master or Slave
mode. Four control bits that configure the framed SPI operation are:
• Framed SPI Support (FRMEN)
The FRMEN bit (SPIxCON2<15>) enables Framed SPI mode and causes the SSx
pin to be
used as a frame synchronization pulse input or output pin. The state of the SSEN bit
(SPIxCON1<7>) is ignored.
• Frame Sync Pulse Direction Control (SPIFSD)
The SPIFSD bit (SPIxCON2<14>) determines whether the SSx
pin is an input or an output
(whether the module receives or generates the frame synchronization pulse).
• Frame Sync Pulse Polarity (FRMPOL)
The FRMPOL bit (SPIxCON2<13>) selects the polarity of the frame synchronization pulse
(active-high or active-low) for a single SPI data frame.
• Frame Sync Pulse Edge Select (FRMDLY)
The FRMDLY bit (SPIxCON2<1>) selects the synchronization pulse to either coincide with,
or precede, the first serial clock pulse.
In Framed Master mode, the SPIx module generates the frame synchronization pulse and
provides this pulse to other devices at the SSx
pin.
In Framed Slave mode, the SPIx module uses a frame synchronization pulse received at the SSx
pin.
The Framed SPI modes are supported in conjunction with the Unframed Master and Slave
modes. As a result, the following four framed SPI configurations are available to the user
application:
• SPI Master mode and Framed Master mode
• SPI Master mode and Framed Slave mode
• SPI Slave mode and Framed Master mode
• SPI Slave mode and Framed Slave mode
These four Framed modes determine whether the SPIx module generates the serial clock and
the frame synchronization pulse.
• When FRMEN (SPIxCON2<15>) = 1 and MSTEN (SPIxCON1<5>) = 1, the SCKx pin
becomes an output and the SPIx clock at SCKx becomes a free-running clock.
• When FRMEN = 1 and MSTEN = 0, the SCKx pin becomes an input. The source clock
provided to the SCKx pin is assumed to be a free-running clock.
The polarity of the clock is selected by the CKP bit (SPIxCON1<6>). The CKE bit (SPIxCON1<8>)
is not used for Framed SPI modes and should be programmed to ‘0’ by the user application.
• When CKP = 0, the frame synchronization pulse output and the SDOx data output change
on the rising edge of the clock pulses at the SCKx pin. Input data is sampled at the SDIx
input pin on the falling edge of the serial clock.
• When CKP = 1, the frame synchronization pulse output and the SDOx data output change
on the falling edge of the clock pulses at the SCKx pin. Input data is sampled at the SDIx
input pin on the rising edge of the serial clock.
Note: The SSx
and SCKx pins must be used in all Framed SPI modes.

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