# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA0XX -- Flash Programming Specification

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© 2008 Microchip Technology Inc. DS39768D-page 31
PIC24FJXXXGA0XX
ICS
(1)
CW1<8> ICD Pin Placement Select bit
11 = ICD EMUC/EMUD pins are shared with PGC1/PGD1
10 = ICD EMUC/EMUD pins are shared with PGC2/PGD2
01 = ICD EMUC/EMUD pins are shared with PGC3/PGD3
00 = Reserved; do not use
IESO CW2<15> Internal External Switchover bit
1 = Two-Speed Start-up enabled
0 = Two-Speed Start-up disabled
IOL1WAY
(1)
CW2<4> IOLOCK Bit One-Way Set Enable bit
0 = The OSCCON<IOLOCK> bit can be set and cleared as needed (provided
an unlocking sequence is executed)
1 = The OSCCON<IOLOCK> bit can only be set once (provided an unlocking
sequence is executed). Once IOLOCK is set, this prevents any possible
future RP register changes
JTAGEN CW1<14> JTAG Enable bit
1 = JTAG enabled
0 = JTAG disabled
OSCIOFNC CW2<5> OSC2 Pin Function bit (except in XT and HS modes)
1 = OSC2 is clock output
0 = OSC2 is general purpose digital I/O pin
SOSCSEL1:
SOSCSEL0
(2)
CW2<12:11> Secondary Oscillator Power Mode Select bits
11 = Default (high drive strength) mode
01 = Low-Power (low drive strength) mode
x0 = Reserved; do not use
POSCMD1:
POSCMD0
CW2<1:0> Primary Oscillator Mode Select bits
11 = Primary oscillator disabled
10 = HS Crystal Oscillator mode
01 = XT Crystal Oscillator mode
00 = EC (External Clock) mode
WDTPOST3:
WDTPOST0
CW1<3:0> Watchdog Timer Prescaler bit
1111 = 1:32,768
1110 = 1:16,384
.
.
.
0001 = 1:2
0000 = 1:1
WDTPRE CW1<4> Watchdog Timer Postscaler bit
1 = 1:128
0 = 1:32
WINDIS CW1<6> Windowed WDT bit
1 = Watchdog Timer in Non-Window mode
0 = Watchdog Timer in Window mode; FWDTEN must be ‘1’
WUTSEL1:
WUTSEL0
(2)
CW2<14:13> Voltage Regulator Standby Mode Wake-up Time Select bits
11 = Default regulator wake time used
01 = Fast regulator wake time used
x0 = Reserved; do not use
TABLE 4-2: PIC24FJXXXGA0XX FAMILY CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field Register Description
Note 1: Available on 28 and 44-pin packages only.
2: Available only on 28 and 44-pin devices with a silicon revision of 3042h or higher.

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