# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA0XX -- Flash Programming Specification

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PIC24FJXXXGA0XX
DS39768D-page 44 © 2008 Microchip Technology Inc.
Step 15: Set the Read Pointer (W6) and load the (next four write) latches.
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
EB0300
000000
BB0BB6
000000
000000
BBDBB6
000000
000000
BBEBB6
000000
000000
BB1BB6
000000
000000
BB0BB6
000000
000000
BBDBB6
000000
000000
BBEBB6
000000
000000
BB1BB6
000000
000000
CLR W6
NOP
TBLWTL [W6++], [W7]
NOP
NOP
TBLWTH.B [W6++], [W7++]
NOP
NOP
TBLWTH.B [W6++], [++W7]
NOP
NOP
TBLWTL [W6++], [W7++]
NOP
NOP
TBLWTL [W6++], [W7]
NOP
NOP
TBLWTH.B [W6++], [W7++]
NOP
NOP
TBLWTH.B [W6++], [++W7]
NOP
NOP
TBLWTL [W6++], [W7++]
NOP
NOP
Step 16: Repeat Steps 14-15, sixteen times, to load the write latches for the 64 instructions.
Step 17: Initiate the programming cycle.
0000
0000
0000
A8E761
000000
000000
BSET NVMCON, #15
NOP
NOP
Step 18: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware.
0000
0000
0000
0000
0000
0001
0000
040200
000000
803B02
883C22
000000
<VISI>
000000
GOTO 0x200
NOP
MOV NVMCON, W2
MOV W2, VISI
NOP
Clock out contents of the VISI register.
NOP
Step 19: Reset the device internal PC.
0000
0000
040200
000000
GOTO 0x200
NOP
Step 20: Repeat Steps 14-19 until all 16 rows of executive memory have been programmed. On the final row, make
sure to initialize the write latches at the Diagnostic and Calibration Words locations with 0xFFFFFF to
ensure that the calibration is not overwritten.
TABLE 5-5: PROGRAMMING THE PROGRAMMING EXECUTIVE (CONTINUED)
Command
(Binary)
Data
(Hex)
Description

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