# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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© 2005-2011 Microchip Technology Inc. DS70157F-page 85
Section 4. Instruction Set Details
Instruction Set
Details
4
4.14.2 MAC Prefetch Register Updates
After the MAC prefetches are made, the effective address stored in each prefetch working register
may be modified. This feature enables efficient single-cycle processing for data stored
sequentially in X and Y memory. Since all DSP instructions execute in Word mode, only even
numbered updates may be made to the effective address stored in the working register.
Allowable address modifications to each prefetch register are -6, -4, -2, 0 (no update), +2, +4 and
+6. This means that effective address updates may be made up to 3 words in either direction.
When the Register Offset Addressing mode is used, no update is made to the base prefetch
register (W9 or W11), or the offset register (W12).
4.14.3 MAC Operations
The mathematical operations performed by the MAC class of DSP instructions center around
multiplying the contents of two working registers and either adding or storing the result to either
Accumulator A or Accumulator B. This is the operation of the MAC, MPY, MPY.N and MSC
instructions.
Table 4-9 shows that W4-W7 must be used for data source operands in the MAC
class of instructions. W4-W7 may be combined in any fashion, and when the same working
register is specified for both operands, a square or square and accumulate operation is
performed.
For the ED and EDAC instructions, the same multiplicand operand must be specified by the
instruction, because this is the definition of the Euclidean Distance operation. Another unique
feature about this instruction is that the values prefetched from X and Y memory are not actually
stored in W4-W7. Instead, only the difference of the prefetched data words is stored in W4-W7.
The two remaining MAC class instructions, CLR and MOVSAC, are useful for initiating or completing
a series of MAC or EDAC instructions and do not use the multiplier. CLR has the ability to clear
Accumulator A or B, prefetch two values from data memory and store the contents of the other
accumulator. Similarly, MOVSAC has the ability to prefetch two values from data memory and store
the contents of either accumulator.
4.14.4 MAC Write Back
The write back ability of the MAC class of DSP instructions facilitates efficient processing of
algorithms. This feature allows one mathematical operation to be performed with one
accumulator, and the rounded contents of the other accumulator to be stored in the same cycle.
As indicated in
Table 4-9, register W13 is assigned for performing the write back, and two
Addressing modes are supported: Direct and Indirect with Post-Increment.
The CLR, MOVSAC and MSC instructions support accumulator Write Back, while the ED, EDAC,
MPY and MPY.N instructions do not support accumulator Write Back. The MAC instruction, which
multiplies two working registers which are not the same, also supports accumulator Write Back.
However, the square and accumulate MAC instruction does not support accumulator Write Back
(see
Table 4-11).
4.14.5 MAC Syntax
The syntax of the MAC class of instructions can have several formats, which depend on the
instruction type and the operation it is performing, with respect to prefetches and accumulator
Write Back. With the exception of the CLR and MOVSAC instructions, all MAC class instructions
must specify a target accumulator along with two multiplicands, as shown in
Example 4-19.
Example 4-19: Base MAC Syntax
Multiply W7*W7, Accumulate to ACCB
; MAC with no prefetch
MAC W4*W5, A
; MAC with no prefetch
MAC W7*W7, B

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