# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Reset

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© 2011 Microchip Technology Inc. DS39712D-page 7-13
Section 7. Reset
Reset
7
7.13 REGISTERS AND STATUS BIT VALUES
Status bits from the RCON and RCON2 registers are set or cleared differently in different Reset
situations, as indicated in Table 7-2.
Table 7-2: Status Bits, Their Significance and the Initialization Condition for the RCON Register
Condition
Program
Counter
TRAPR
IOPUWR
DPSLP
EXTR
SWR
WDTO
(1)
SLEEP
(2)
IDLE
(2)
CM
BOR
POR
VBAT
(6)
VBPOR
(6)
VDDPOR
(6)
VDDBOR
(6)
Power-on Reset 000000h 0 0 0 0 0 0 0 0 0 1 1 u 1
(7)
1 1
RESET Instruction 000000h u u u u 1 u u u u u u u u u u
Brown-out Reset 000000h 0 0 u u 0 0 0 0 0 1 u u u u 1
MCLR during Run Mode 000000h u u u 1 u u u u u u u u u u u
MCLR during Idle Mode 000000h u u u 1 u 0
(1)
u 1
(2)
u u u u u u u
MCLR
during Sleep Mode 000000h u u u 1 u 0
(1)
1
(2)
u u u u u u u u
MCLR during Deep Sleep Mode
(3)
000000h 0 0 1 1 0 0 0 0 0 1 1 u u 1 1
WDT Time-out Reset during Run
Mode
000000h u u u u u 1 u u u u u u u u u
WDT Time-out Reset during Idle
Mode
PC + 2 u u u u u 1 u 1
(2)
u u u u u u u
WDT Time-out Wake-up during
Sleep Mode
PC + 2 u u u u u 1 1
(2)
u u u u u u u u
Trap Event Reset 000000h 1 u u u u u u u u u u u u u u
Illegal Opcode/
Uninitialized WREG
000000h u 1 u u u u u u u u u u u u u
Configuration Word
Mismatch Reset
000000h u u u u u u u u 1 u u u u u u
Interrupt Exit from Idle Mode
(4)
PC + 2
(5)
u u u u u u u 1
(2)
u u u u u u u
Interrupt Exit from Sleep Mode
(4)
PC + 2
(5)
u u u u u 0
(2)
1
(2)
u u u u u u u u
Idle Mode
(execute PWRSAV 1)
PC + 2 u u u u u u u 1 u u u u u u u
Sleep Mode
(execute PWRSAV 0)
PC + 2 u u u u u u 1 u u u u u u u u
Deep Sleep Mode
(set DSEN and execute PWRSAV 0)
(3)
000000h 0 0 1 0 0 0 0 0 0 1 1 u u 1 1
Wake from Battery Backup with
Continuous VBAT
000000h 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1
Wake from V
BAT mode with
Discontinuous V
BAT source
000000h 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1
Power-on Reset on V
DD 000000h 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1
Legend: u = unchanged
Note 1: The PWRSAV instruction also clears the WDTO bit.
2: The state of the SLEEP and IDLE bits is defined by the previously executed PWRSAV instruction.
3: Select PIC24F devices only.
4: An interrupt’s priority should not be changed while the interrupt is enabled. If a priority change is needed,
clear the associated interrupt enable bit, select the new priority and set the interrupt to enable it.
5: The Program Counter (PC) is loaded with PC + 2 if the interrupt priority is less than, or equal to, the CPU
interrupt priority level. The PC is loaded with the hardware vector address if the interrupt priority is greater
than the CPU interrupt priority level.
6: This bit is not implemented on all devices. Consult the device family data sheet for more information.
7: This bit is set on the first POR; after that, it is set on V
BAT POR events.

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