# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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DS70000195F-page 52  2007-2014 Microchip Technology Inc.
Figure 7-11: Slave Message (Write Data to Slave: 7-Bit Address; Address Matches; A10M = 0; GCEN = 0; IPMIEN = 0; AHEN =
STRICT = 0 and BOEN = 0)
1
Slave recognizes Start event; S and P status bits set/clear accordingly.
SCLx (Master)
SDAx (Master)
SCLx (Slave)
SDAx (Slave)
I2CxRCV
RBF
SI2CxIF
STREN
1 2 3 4 5 6 7 8
A2 A1
9
A
D7 D6 D5 D4 D3 D2 D1
1 2 3 4 5 6 7 8 9
1 3
2
A
4 3 3
2
Slave receives address byte. Address matches. Slave Acknowledges
3
Next received byte is message data. The byte moved to the I2CxRCV register sets the RBF status bit.
4
User software reads the I2CxRCV register. RBF status bit clears.
5
Slave recognizes Stop event; S and P status bits set/clear accordingly.
Slave generates interrupt. Slave Acknowledges reception.
A7 A6 A5 A4 A3
S
P
I2COV
R/W
D/A
D7 D6 D5 D4 D3 D2 D1
1 2 3 4 5 6 7 8 9
A
D7 D6 D5 D4 D3 D2 D1
1 2 3 4 5 6 7 8 9
A
D7 D6 D5 D4 D3
1 2 3 4 5
SCLREL
4 4
and generates interrupt. Address byte is moved to I2CxRCV register and must be read by user software to prevent buffer overflow.
D0D0
D0
W
SI2CxIF Interrupt Flag Cleared by User Software

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