# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Data Memory

- 1
- 2
- 3
- 4
…
- 7
- 8

PIC24F Family Reference Manual
DS39717A-page 3-2 Advance Information © 2007 Microchip Technology Inc.
3.1 INTRODUCTION
As Harvard architecture devices, PIC24F microcontrollers feature separate program and data
memory spaces and busses. The PIC24F architecture also allows the direct access of program
memory from the data space during code execution.
3.2 DATA MEMORY ORGANIZATION
3.2.1 Data Address Space
The PIC24F core has a 16-bit wide data memory space, addressable as a single linear range.
The data space is accessed using two Address Generation Units (AGUs), one each for read and
write operations. The data space memory map is shown in Figure 3-1.
All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within
the data space. This gives a data space address range of 64 Kbytes or 32K words. The lower
32 Kbytes of the data memory space (that is, when EA<15> = 0) is used for implemented mem-
ory addresses, while the upper half (EA<15> = 1) is reserved for the Program Space Visibility
(PSV) area. For details on PSV, refer to Section 4.4 “Program Space Visibility from Data
Space”.
3.2.2 Data Space Width
The data memory space is organized in byte addressable, 16-bit wide blocks. Data is aligned in
data memory and registers as 16-bit words, but all the data space EAs resolve to bytes. The
Least Significant Bytes of each word have even addresses, while the Most Significant Bytes have
odd addresses.
Note 1: Please refer to the specific device data sheet for actual implementation of data
memory in a specific device.
2: Should an EA point to a location outside of the physically implemented data
memory area in a device, an all zero word or byte will be returned.

- 1
- 2
- 3
- 4
…
- 7
- 8