# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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 2007-2014 Microchip Technology Inc. DS70000195F-page 25
Inter-Integrated Circuit™ (I
2
C™)
5.3.1 RBF STATUS FLAG
When receiving a data, the RBF status bit (I2CxSTAT<1>) is set when a device address or data
byte is loaded into the I2CxRCV register from the I2CxRSR register. It is cleared when the user
software reads the I2CxRCV register.
5.3.2 I2COV STATUS FLAG
If another byte is received in the I2CxRSR register while the RBF status bit remains set, and the
previous byte remains in the I2CxRCV register, the I2COV status bit (I2CxSTAT<6>) is set and
the data in the I2CxRSR register is lost.
Leaving the I2COV status bit set does not inhibit further reception. If the RBF status bit is cleared
by reading the I2CxRCV register, and the I2CxRSR register receives another byte, that byte will
be transferred to the I2CxRCV register.
5.3.3 IWCOL STATUS FLAG
If the user software writes the I2CxTRN register when a receive is already in progress (that is,
the I2CxRSR register is still shifting in a data byte), the IWCOL status bit (I2CxSTAT<7>) is set
and the contents of the buffer are unchanged (the write does not occur).
Note: Because queuing of events is not allowed, writing to the lower 5 bits of the I2CxCON
register is disabled until the data reception condition is complete.

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