# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004

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 2010-2013 Microchip Technology Inc. DS39881E-page 267
PIC24FJ64GA004 FAMILY
APPENDIX A: REVISION HISTORY
Revision A (March 2007)
Original data sheet for the PIC24FJ64GA004 family of
devices.
Revision B (March 2007)
Changes to Table 26-8; packaging diagrams updated.
Revision C (January 2008)
 Update of electrical specifications to include DC
characteristics for Extended Temperature
devices.
 Update for A/D converter chapter to include
information on internal band gap voltage
reference.
 Added Appendix B: “Additional Guidance for
PIC24FJ64GA004 Family Applications”.
 General revisions to incorporate corrections
included in document errata to date (DS80333).
Revision D (January 2010)
 Update of electrical specifications to include 60°C
specifications for power-down current to DC
characteristics.
 Removes references to JTAG programming
throughout the document.
 Other minor typographic corrections throughout.
Revision E (May 2013)
 Updates all pin diagrams to indicate 5V tolerant
pins.
 Updates all package labeling diagrams.
 Changes the VREGS bit name (RCON<8>) to
PMSLP in all occurrences throughout the data
sheet; also updates the description of the bits
functionality in Register 6-1. (The actual operation
of the bit remains unchanged.)
 Adds additional explanatory text to the following
sections:
- Section 9.2.1 ”Sleep Mode”
- Section 10.4.2.1 ”Peripheral Pin Select
Function Priority”
- Section 24.2.3 ”On-Chip Regulator and
POR”
 Updates Section 2.0 “Guidelines for Getting
Started with 16-Bit Microcontrollers” with the
most current information on V
CAP selection.
 Replaces Table 6-3 (Reset Delay Times) with an
updated version.
 Updates Section 7.0 ”Interrupt Controller” by
adding a description of the INTTREG register
(Register 7-31).
 Updates Section 8.0 ”Oscillator Configuration”
by correcting the external oscillator inputs in
Figure 8-1 and a new unlock code sequence in
Example 8-1.
 Replaces Example 10-2 with a new code example.
 Updates Section 19.0 ”Real-Time Clock and
Calendar (RTCC)” to add introductory text and
amend input sources in Figure 19-1.
 Updates Section 20.0 ”Programmable Cyclic
Redundancy Check (CRC) Generator” with a
more current version (no technical changes to the
module or its operation).
 Updates
Section 26.0 ”Instruction Set Summary”
:
- Updates syntax of ASR, DAW, LSR, MOV
and SL instructions to conform with the
Programmer’s Reference Manual
- Adds previously omitted instruction, FBCL
 Adds to
Section 27.0 ”Electrical Characteristics”
:
- New Specification DC18 (VBOR) to Table 27-3
- New Specifications DI60a (I
ICL), DI60b (IICH)
and DI60c (I
ICT) to Table 27-7
- New Table 27-10 (Comparator Specifications)
and Table 27-11 (Comparator Voltage Refer-
ence Specifications); previous Table 27-10 is
now renumbered as Table 27-12, and all
subsequent tables renumbered accordingly
- New Table 27-17 (Internal RC Oscillator
Specifications)
- New specifications, AD08 (I
VREF), AD09
(Z
REF) and AD13 (Leakage Current), to
Table 27-20
- Combines previous Table 27-15 (AC Charac-
teristics: Internal RC Accuracy) and
Table 27-16 (Internal RC Accuracy) into a
new Table 27-18 (AC Characteristics: Internal
RC Accuracy)
 Other minor typographic corrections throughout.

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