# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- UART

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 2009-2013 Microchip Technology Inc. DS70000582E-page 7
UART
Register 2-2: UxSTA: UARTx Status and Control Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-1
UTXISEL1 UTXINV UTXISEL0 URXEN
(1)
UTXBRK UTXEN
(2)
UTXBF TRMT
(3)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0
URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA
bit 7 bit 0
Legend: C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
bit 15,13 UTXISEL<1:0>: UARTx Transmission Interrupt Mode Selection bits
11 = Reserved
10 = Interrupt is generated when a character is transferred to the Transmit Shift Register (TSR) and
the transmit buffer becomes empty
01 = Interrupt is generated when the last transmission is over, transmit buffer is empty (i.e., the last
character has been shifted out of the Transmit Shift Register) and all the transmit operations are
completed
00 = Interrupt is generated when any character is transferred to the Transmit Shift Register and the
transmit buffer is empty (which implies at least one location is empty in the transmit buffer)
bit 14 UTXINV: UARTx Transmit Polarity Inversion bit
IREN =
0:
1 = UxTX Idle state is 0
0 = UxTX Idle state is 1
IREN = 1:
1 = IrDA
®
is encoded, UxTX Idle state is 1
0 = IrDA is encoded, UxTX Idle state is 0
bit 12 URXEN: UARTx Receive Enable bit
(1)
1 = Receive is enabled, UxRX pin is controlled by UARTx
0 = Receive is disabled, UxRX pin is controlled by the port
bit 11 UTXBRK: UARTx Transmit Break bit
1 = UxTX pin is driven low regardless of the transmitter state (Sync Break transmission  Start bit is
followed by twelve 0s and a Stop bit)
0 = Sync Break transmission is disabled or complete
bit 10 UTXEN: UARTx Transmit Enable bit
(2)
1 = UARTx transmitter is enabled; UxTX pin is controlled by UARTx (if UARTEN = 1)
0 = UARTx transmitter is disabled; any pending transmission is aborted and the buffer is reset, UxTX
pin is controlled by the port
bit 9 UTXBF: UARTx Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full; at least one more data word can be written
bit 8 TRMT: Transmit Shift Register is Empty bit (read-only)
(3)
1 = Transmit Shift Register is empty and the transmit buffer is empty (i.e., the last transmission has
completed)
0 = Transmit Shift Register is not empty; a transmission is in progress or queued in the transmit buffer
Note 1: This bit is only available in devices supporting Smart Card. Refer to the “Universal Asynchronous
Receiver Transmitter (UART)” chapter of the specific device data sheet for availability.
2: Enable the UARTEN bit (UxMODE<15>) before enabling this bit.
3: User software should wait at least one instruction cycle between writing UxTXREG and reading the TRMT bit.

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