# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- 10-Bit ADC

- 1
- 2
…
- 25
- 26
- 27
- 28
- 29
…
- 57
- 58

© 2010 Microchip Technology Inc. Preliminary DS39737A-page 49-27
Section 49. 10-Bit ADC with 4 Simultaneous Conversions
10-Bit ADC with
4 Simultaneous
Conversions
49
49.6.2 Alternate Input Selection Mode
In an Alternate Input Selection mode, the MUXA and MUXB control bits select the channel for
conversion. The ADC completes one sweep using the MUXA selection, and then another sweep
using the MUXB selection, and then another sweep using the MUXA selection, and so on. The
Alternate Input Selection mode is enabled by setting the Alternate Sample bit (ALTS) in the ADC
Control Register 2 (ADxCON2<0>).
The analog input multiplexer is controlled by the AD1CHS123 and AD1CHS0 registers. There
are two sets of control bits, designated as MUXA (CHySA/CHyNA) and MUXB (CHySB/CHyNB),
to select a particular input source for conversion. The MUXB control bits are used in Alternate
Input Selection mode.
Table 49-9: Analog Input Selection
For Alternate Input Selection mode, an ADC interrupt must be generated after an even number
of sample/conversion sequences by programming the Samples Convert Sequences Per
Interrupt bits (SMPI<3:0>). Table 49-10 lists the valid SMPI values for Alternate Input Selection
mode in different ADC configurations.
Table 49-10: Valid SMPI Values for Alternate Input Selection Mode
Example 49-4 shows the code sequence to set up the ADC module for Alternate Input Selection
mode in the 4-channel simultaneous sampling configuration. Figure 49-14 illustrates the ADC
module operation sequence.
MUXA MUXB
Control bits Analog Inputs Control bits Analog Inputs
CH0 +ve CH0SA<4:0> AN0 to AN5 CH0SB<4:0> AN0 to AN5
-ve CH0NA AVss, AN1 CH0NB AV
SS, AN1
CH1 +ve CH123SA AN0, AN3 CH123SB AN0, AN3
-ve CH123NA<1:0> AVss CH123NB<1:0> AVss
CH2 +ve CH123SA AN1, AN4 CH123SB AN1, AN4
-ve CH123NA<1:0> AVss CH123NB<1:0> AVss
CH3 +ve CH123SA AN2, AN5 CH123SB AN2, AN5
-ve CH123NA<1:0> AVss CH123NB<1:0> AVss
Note: Not all inputs are present on all devices.
CHPS<1:0> SIMSAM
SMPI<3:0>
(Decimal)
Conversions/
Interrupts
Description
00 x 1,3,5,7,9,11,13,15 2,4,6,8,10,12,14,16 1-Channel mode
01 0 3,7,11,15 4,8,12,16 2-Channel Sequential
Sampling mode
1x 0 7,15 8,16 4-Channel Sequential
Sampling mode
01 1 1,3,5,7 4,8,12,16 2-Channel Simultaneous
Sampling mode
1x 1 1,3 8,16 4-Channel Simultaneous
Sampling mode
Note: On ADC interrupt, the ADC internal logic is initialized to restart the conversion
sequence from the beginning.

- 1
- 2
…
- 25
- 26
- 27
- 28
- 29
…
- 57
- 58