# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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 2007-2014 Microchip Technology Inc. DS70000195F-page 59
Figure 7-16: Slave Message (Read Data from Slave: 10-Bit Address)
1 Slave recognizes Start event, S and P bits set/clear accordingly.
SCLx (Master)
SDAx (Master)
SCxL (Slave)
SDAx (Slave)
I2CxTRN
TBF
I2CxRCV
RBF
SI2CxIF
STREN
1 2 3 4 5 6 7 8 9
A
1 42 7 8
2 Slave receives first address byte. Write indicated. Slave Acknowledges and
6
User software writes I2CxTRN with response data.
8 At the end of ninth clock, if master sent ACK, module clear
Slave recognizes Stop event, S and P bits set/clear accor
S
P
ADD10
R/W
D/A
SCLREL
5 6
D7D6D5
1 2 3
3 6 7
7 User software sets SCLREL to release clock hold. Master
slave transmits data byte.
clock. Slave generates interrupt.
9 At the end of ninth clock, if master sent NACK, no mor
does not suspend clock or generate interrupt.
A7A6A5A4 A3A2A1
1 2 3 4 5 6 7 8 9
A
A9A8
1 1 1 1
0
1 2 3 4 5 6 7 8 9
A
A9A8
1 1 1 1
0
D7D6D5D4D3D2D1
1 2 3 4 5 6 7 8 9
A
3 Slave receives address byte. Address matches. Slave Acknowledges and
10
4
Master sends a Repeated Start to redirect the message.
5
Slave receives re-send of first address byte. User software reads I2CxRCV register.
R
generates interrupt. User software reads I2CxRCV register.
generates interrupt. User software reads I2CxRCV register.
Read indicated. Slave suspends clock.
D0
A0
W

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