# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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© 2005-2011 Microchip Technology Inc. DS70157F-page 343
Section 5. Instruction Descriptions
Instruction
Descriptions
5
Example 2:
PUSH [W5+W10] ; Push [W5+W10] to TOS
Before
Instruction
After
Instruction
W5 1200 W5 1200
W10 0044 W10 0044
W15 0806 W15 0808
Data 0806 216F Data 0806 B20A
Data 1244 B20A Data 1244 B20A
SR 0000 SR 0000
PUSH.D
Double Push Wns:Wns+1 to TOS
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} PUSH.D Wns
Operands: Wns ∈ [W0, W2, W4 ... W14]
Operation: (Wns) → (TOS)
(W15) + 2 → W15
(Wns + 1) → (TOS)
(W15) + 2 → W15
Status Affected: None
Encoding:
1011 1110 1001 1111 1000 sss0
Description: A double word (Wns:Wns + 1) is PUSHed to the Top-of-Stack (TOS).
The least significant word (Wns) is PUSHed to the TOS first, and the
most significant word (Wns + 1) is PUSHed to the TOS last. Since a
double word is PUSHed, the Stack Pointer (W15) gets incremented by 4.
The ‘s’ bits select the address of the source register pair.
Note 1: This instruction operates on double words. See
Figure 4-3 for
information on how double words are aligned in memory.
2: Wns must be an even working register.
3: This instruction is a specific version of the “MOV.D Wns, Wd”
instruction (MOV.D Wns, [W15++]). It reverse assembles
as MOV.D.
Words: 1
Cycles: 2
Example 1:
PUSH.D W6 ; Push W6:W7 to TOS
Before
Instruction
After
Instruction
W6 C451 W6 C451
W7 3380 W7 3380
W15 1240 W15 1244
Data 1240 B004 Data 1240 C451
Data 1242 0891 Data 1242 3380
SR 0000 SR 0000

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