# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004

- 1
- 2
…
- 133
- 134
- 135
- 136
- 137
…
- 277
- 278

 2010-2013 Microchip Technology Inc. DS39881E-page 135
PIC24FJ64GA004 FAMILY
14.0 OUTPUT COMPARE
14.1 Setup for Single Output Pulse
Generation
When the OCM<2:0> control bits (OCxCON<2:0>) are
set to 100, the selected output compare channel
initializes the OCx pin to the low state and generates a
single output pulse.
To generate a single output pulse, the following steps
are required (these steps assume the timer source is
initially turned off, but this is not a requirement for the
module operation):
1. Determine the instruction clock cycle time. Take
into account the frequency of the external clock
to the timer source (if one is used) and the timer
prescaler settings.
2. Calculate the time to the rising edge of the output
pulse relative to the TMRy start value (0000h).
3. Calculate the time to the falling edge of the pulse
based on the desired pulse width and the time to
the rising edge of the pulse.
4. Write the values computed in Steps 2 and 3
above into the Output Compare x register,
OCxR, and the Output Compare x Secondary
register, OCxRS, respectively.
5. Set the Timery Period register, PRy, to a value
equal to or greater than the value in OCxRS, the
Output Compare x Secondary register.
6. Set the OCMx bits to 100 and the OCTSEL
(OCxCON<3>) bit to the desired timer source.
The OCx pin state will now be driven low.
7. Set the TON (TyCON<15>) bit to 1, which
enables the compare time base to count.
8. Upon the first match between TMRy and OCxR,
the OCx pin will be driven high.
9. When the incrementing timer, TMRy, matches the
Output Compare x Secondary register, OCxRS,
the second and trailing edge (high-to-low) of the
pulse is driven onto the OCx pin. No additional
pulses are driven onto the OCx pin and it remains
at low. As a result of the second compare match
event, the OCxIF interrupt flag bit is set, which
will result in an interrupt if it is enabled, by
setting the OCxIE bit. For further information
on peripheral interrupts, refer to Section 7.0
“Interrupt Controller”.
10. To initiate another single pulse output, change the
Timer and Compare register settings, if needed,
and then issue a write to set the OCMx bits to
100. Disabling and re-enabling the timer and
clearing the TMRy register are not required, but
may be advantageous for defining a pulse from a
known event time boundary.
The output compare module does not have to be dis-
abled after the falling edge of the output pulse. Another
pulse can be initiated by rewriting the value of the
OCxCON register.
14.2 Setup for Continuous Output
Pulse Generation
When the OCM<2:0> control bits (OCxCON<2:0>) are
set to 101, the selected output compare channel initial-
izes the OCx pin to the low state and generates output
pulses on each and every compare match event.
For the user to configure the module for the generation
of a continuous stream of output pulses, the following
steps are required (these steps assume the timer
source is initially turned off, but this is not a requirement
for the module operation):
1. Determine the instruction clock cycle time. Take
into account the frequency of the external clock
to the timer source (if one is used) and the timer
prescaler settings.
2. Calculate the time to the rising edge of the output
pulse relative to the TMRy start value (0000h).
3. Calculate the time to the falling edge of the pulse
based on the desired pulse width and the time to
the rising edge of the pulse.
4. Write the values computed in Steps 2 and 3 above
into the Output Compare x register, OCxR, and
the Output Compare x Secondary register,
OCxRS, respectively.
5. Set the Timery Period register, PRy, to a value
equal to or greater than the value in OCxRS.
6. Set the OCMx bits to 101 and the OCTSEL bit to
the desired timer source. The OCx pin state will
now be driven low.
7. Enable the compare time base by setting the TON
(TyCON<15>) bit to 1.
8. Upon the first match between TMRy and OCxR,
the OCx pin will be driven high.
9. When the compare time base, TMRy, matches the
OCxRS, the second and trailing edge (high-to-low)
of the pulse is driven onto the OCx pin.
10. As a result of the second compare match event,
the OCxIF interrupt flag bit set.
11. When the compare time base and the value in its
respective Timery Period register match, the
TMRy register resets to 0x0000 and resumes
counting.
12. Steps 8 through 11 are repeated and a continuous
stream of pulses is generated indefinitely. The
OCxIF flag is set on each OCxRS/TMRy compare
match event.
Note: This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
“Output Compare” (DS39706).

- 1
- 2
…
- 133
- 134
- 135
- 136
- 137
…
- 277
- 278