# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Watchdog Timer

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© 2010 Microchip Technology Inc. DS39697B-page 9-3
Section 9. Watchdog Timer (WDT)
Watchdog Timer
(WDT)
9
9.2 WDT OPERATION
When enabled, the WDT will increment until it overflows or “times out”. A WDT time-out will force
a device Reset, except during Sleep or Idle modes. To prevent a WDT Time-out Reset, the user
must periodically clear the Watchdog Timer using the instructions, PWRSAV or CLRWDT. If the
WDT times out during Sleep or Idle modes, the device will wake-up and continue code execution
from where the PWRSAV instruction was executed.
In either case, the WDTO bit (RCON<4>) will be set to indicate that the device Reset or wake-up
event was due to a WDT time-out. If the WDT wakes the CPU from Sleep or Idle mode, the
SLEEP status bit (RCON<3>) or IDLE status bit (RCON<2>) will also be set to indicate that the
device was previously in a Power-Saving mode.
9.2.1 Enabling and Disabling the WDT
The WDT is enabled or disabled by the FWDTEN (CW1<7>) Configuration bit. When the
FWDTEN Configuration bit is set, the WDT is enabled. This is the default value for an erased
device. Refer to the device data sheet for further details on the Flash Configuration Word
registers.
9.2.2 Software Controlled WDT
If the FWDTEN Configuration bit is set, the WDT is always enabled. However, the WDT can be
optionally controlled in the user software when the FWDTEN Configuration bit has been
programmed to ‘0’.
The WDT is enabled in software by setting the SWDTEN control bit (RCON<5>). The SWDTEN
control bit is cleared on any device Reset. The software WDT option allows the user to enable
the WDT for critical code segments and disable the WDT during non-critical segments for
maximum power savings.
9.2.3 WDT Window
The Watchdog Timer has an optional Windowed mode enabled by programming the WINDIS
Configuration bit (CW1<6>) to ‘0’. In the Windowed mode, the CLRWDT instruction must occur
within the allowed window of the WDT period. Any CLRWDT instruction that occurs within the
disallowed window of the WDT period will cause a WDT Reset, similar to a WDT time-out.
Some devices have the selectable window bits, WDTWIN<1:0>. Table 9-1 lists all possible
window options for devices with and without the WDTWIN<1:0> bits.
Table 9-1: Window Bit Options
Note: Refer to the specific device data sheet for details on the RCON register bits.
Note: The WDT must be enabled (FWDTEN = 1) to use WDT Windowed mode.
WDTWIN<1:0> Selected Allowed Window
Bits not implemented 25%
11 25%
10 37.50%
01 50%
00 75%

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