# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Reset

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© 2011 Microchip Technology Inc. DS39712D-page 7-9
Section 7. Reset
Reset
7
7.7 BROWN-OUT RESET (BOR)
When the on-chip regulator is enabled, PIC24F family devices have a simple brown-out capability.
BOR is applicable only when the regulator is enabled. If the voltage supplied to the regulator is
inadequate to maintain the tracking level, the regulator Reset circuitry will generate a Brown-out
Reset. This event is captured by the BOR flag bit (RCON<0>).
Refer to Section 7.16 “Electrical Specifications” for further details.
7.7.1 Voltage Regulator Tracking Mode and Low-Voltage Detection
When enabled, the on-chip regulator provides a constant voltage to the digital core logic.
(1,2)
In order to prevent “brown-out” conditions when the voltage drops too low for the regulator, the
regulator enters Tracking mode. In Tracking mode, the regulator output follows V
DD with a typical
voltage drop of 100 mV. When the device enters Tracking mode, it is no longer possible to oper-
ate at full speed. To provide information about when the device enters Tracking mode, the
on-chip regulator includes a simple, Low-Voltage Detect (LVD) circuit. When V
DD drops below
full-speed operating voltage, the circuit sets the Low-Voltage Detect Interrupt Flag, LVDIF
(IFS4<8>). This can be used to generate an interrupt and put the application into a Low-Power
Operational mode or trigger an orderly shutdown. Low-Voltage Detection is only available when
the regulator is enabled.
7.7.2 Detecting BOR
When the BOR is enabled, the BOR bit (RCON<1>) is always reset to ‘1’ on any BOR or POR
event. This makes it difficult to determine if a BOR event has occurred just by reading the state
of BOR alone. A more reliable method is to simultaneously check the state of both POR and
BOR. This assumes that the POR bit is reset to ‘0’ in the software immediately after any POR
event. If the BOR bit is ‘1’ while POR is ‘0’, it can be reliably assumed that a BOR event has
occurred.
7.7.3 Deep Sleep BOR (DSBOR) (Select Devices Only)
For devices with Deep Sleep capability, an independent Deep Sleep BOR (DSBOR) circuit pro-
vides simple BOR/POR protection during Deep Sleep operation. Rather than trigger a Reset in
its own right, the DSBOR re-arms the regular POR circuit to ensure a device Reset if VDD drops
below the POR threshold during Deep Sleep operation.
The DSBOR operates on a single trip point of 2.0V, nominal. Because it is designed for very
low-current consumption, its accuracy may vary.
DSBOR events (BOR and POR) are monitored through the DSCON and DSWAKE registers,
respectively. Refer to Section 39. “Power-Saving Features with Deep Sleep” for a more
detailed discussion.
The DSBOR circuit can be selectively enabled or disabled using the DSBOREN Configuration
bit. By default, the circuit is enabled.
Note 1: Some devices have constantly enabled regulators. Refer to the specific device data
sheet for more information.
2: Refer to the device data sheet for the specific regulator voltage.
Note: As with other BOR events in other power-saving modes, both the POR and BOR are
set when the device exits from the Deep Sleep mode.

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