# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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© 2005-2011 Microchip Technology Inc. DS70157F-page 265
Section 5. Instruction Descriptions
Instruction
Descriptions
5
LAC
Load Accumulator
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X
Syntax: {label:} LAC Ws, {#Slit4,} Acc
[Ws],
[Ws++],
[Ws--],
[--Ws],
[++Ws],
[Ws+Wb],
Operands:
Ws ∈ [W0 ... W15]
Wb ∈ [W0 ... W15]
Slit4 ∈ [-8 ... +7]
Acc ∈ [A,B]
Operation:
Shift
Slit4
(Extend(Ws)) → Acc(A or B)
Status Affected:
OA, OB, OAB, SA, SB, SAB
Encoding:
1100 1010 Awww wrrr rggg ssss
Description: Read the contents of the source register, optionally perform a signed 4-bit
shift and store the result in the specified accumulator. The shift range is -8:7,
where a negative operand indicates an arithmetic left shift and a positive
operand indicates an arithmetic right shift. The data stored in the source
register is assumed to be 1.15 fractional data and is automatically
sign-extended (through bit 39) and zero-backfilled (bits [15:0]), prior to
shifting.
The ‘A’ bit specifies the destination accumulator.
The ‘w’ bits specify the offset register Wb.
The ‘r’ bits encode the accumulator pre-shift.
The ‘g’ bits select the source Address mode.
The ‘s’ bits specify the source register Ws.
Note: If the operation moves more than sign-extension data into the
upper Accumulator register (AccxU), or causes a saturation, the
appropriate overflow and saturation bits will be set.
Words:
1
Cycles:
1
(1)
Note 1:
In dsPIC33E and PIC24E devices, the listed cycle count does not apply to read and
read-modify-write operations on non-CPU Special Function Registers. For more
details, see
Note 3
in
Section 3.2.1 “Multi-Cycle Instructions”
.

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