# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004

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 2010-2013 Microchip Technology Inc. DS39881E-page 163
PIC24FJ64GA004 FAMILY
bit 4 RXINV: Receive Polarity Inversion bit
1 = UxRX Idle state is 0
0 = UxRX Idle state is 1
bit 3 BRGH: High Baud Rate Enable bit
1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)
0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode)
bit 2-1 PDSEL<1:0>: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0 STSEL: Stop Bit Selection bit
1 = Two Stop bits
0 = One Stop bit
REGISTER 17-1: UxMODE: UARTx MODE REGISTER (CONTINUED)
Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See
Section 10.4 “Peripheral Pin Select (PPS)” for more information.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
3: Bit availability depends on pin availability.

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