# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 -- UART

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 2009-2013 Microchip Technology Inc. DS70000582E-page 33
UART
11.0 UART OPERATION DURING CPU SLEEP AND IDLE MODES
11.1 UART Operation in Sleep Mode
When the device enters Sleep mode, all clock sources supplied to the UART module are shut
down and stay at logic 0. If the device enters Sleep mode in the middle of a UART transmission
or reception operation, the operation is aborted and the UARTx pins (BCLKx, UxRTS and UxTX)
are driven to the default state.
A Start bit, when detected on the UARTx Receive pin (UxRX), can wake up the device from Sleep
mode if the WAKE bit (UxMODE<7>) is set just before the device enters Sleep mode. In this
mode, if the UARTx Receive Interrupt (UxRXIE) is enabled, a falling edge on the UART receive
pin generates a UARTx Receive Interrupt Flag (UxRXIF).
The receive interrupt wakes up the device from Sleep and the following events occur:
 If the assigned priority for the interrupt is less than or equal to the current CPU priority, the
device wakes up and continues code execution from the instruction following the PWRSAV
instruction that initiated Sleep mode.
 If the assigned priority level for the interrupt source is greater than the current CPU priority,
the device wakes up and the CPU execution process begins. Code execution continues
from the first instruction of the captured ISR.
 The UART does not recognize the first character received after a wake from Sleep due to
the delay in restoration of the clocks after the oscillator restart.
The WAKE bit is automatically cleared when a low-to-high transition is observed on the UxRX
line following the wake-up event.
11.2 UART Operation in Idle Mode
 When the device enters Idle mode, the system clock sources remain functional, but the
CPU stops code execution. The UART Stop in Idle bit (USIDL) in the UARTx Mode register
(UxMODE<13>) determines whether the module stops in Idle mode or continues to operate
in Idle mode.
 If USIDL = 0, the module continues to operate in Idle mode and provides full functionality.
 If USIDL = 1, the module stops in Idle mode. The module performs the same functions
when stopped in Idle mode as in Sleep mode (refer to Section 11.1 “UART Operation in
Sleep Mode”).
11.3 Auto-Wake-up on Sync Break Character
The auto-wake-up feature is enabled with the WAKE bit (UxMODE<7>). Once WAKE is active,
the typical receive sequence on UxRX is disabled. Following the wake-up event, the module
generates the UxRXIF interrupt.
The LPBACK bit (UxMODE<6>) must equal 0 for wake-up to operate.
A wake-up event consists of a high-to-low transition on the UxRX line. This coincides with the
start of a Sync Break or a Wake-up Signal character for the LIN/J2602 protocol. When WAKE is
active, the UxRX line is monitored independently from the CPU mode. The UxRXIF interrupt will
be generated synchronously to the Q clocks in normal user mode, and asynchronously, if the
module is disabled due to Sleep or Idle mode. To assure that no actual data is lost, the WAKE bit
should be set just prior to entering the Sleep mode and while the UART module is in Idle.
The WAKE bit is automatically cleared once a low-to-high transition is observed on the UxRX line
following the wake-up event. At this point, the UART module is in Idle mode and is returned to
normal operation. This signals to the user that the Sync Break event is over. If the user clears the
WAKE bit prior to sequence completion, unexpected module behavior can result.

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