# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Motor Control PWM

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PIC24F Family Reference Manual
DS39735A-page 47-14 Preliminary © 2010 Microchip Technology Inc.
Register 47-11: PxOVDCON: Override Control Register
Register 47-12: PxDC1: PWM Duty Cycle Register 1
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
  POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
  POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as 0
bit 13-8 POVD3H:POVD1L: PWM Output Override bits
1 = Output on PWMxH3:PWMxH1/PWMxL3:PWMxL1 I/O pin pair is controlled by the PWM generator
0 = Output on PWMxH3:PWMxH1/PWMxL3:PWMxL1 I/O pin pair is driven, controlled by the value in the
corresponding POUT3H:POUT1H/POUT3L:POUT1L bit
bit 7-6 Unimplemented: Read as 0
bit 5-0 POUT3H:POUT1L: PWM Manual Output bits
1 = PWMxH3:PWMxH1/PWMxL3:PWMxL1 I/O pin pair is driven active when the corresponding
POVD3H:POVD1H/POVD3L:POVD1L bit is cleared
0 = PWMxH3:PWMxH1/PWMxL3:PWMxL1 I/O pin pair is driven inactive when the corresponding
POVD3H:POVD1H/POVD3L:POVD1L bit is cleared
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PxDC115 PxDC114 PxDC113 PxDC112 PxDC111 PxDC110 PxDC19 PxDC18
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PxDC17 PxDC16 PxDC15 PxDC14 PxDC13 PxDC12 PxDC11 PxDC10
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
bit 15-0 PxDC1<15:0>: PWM Duty Cycle 1 Value bits

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