# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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 2007-2014 Microchip Technology Inc. DS70000195F-page 63
Inter-Integrated Circuit™ (I
2
C™)
9.0 OPERATION IN POWER-SAVING MODES
9.1 Sleep Mode in Slave Mode
The I
2
C module can wake-up from Sleep mode on detecting a valid slave address match.
Because all bit shifting is done with reference to the external SCLx signal, generated by an I
2
C
master, transmissions and receptions can continue even while in Sleep mode.
9.2 Sleep Mode in Master Mode
If Sleep occurs in the middle of a master transmission, and the state machine is partially into a
transmission as the clocks stop, the behavior of the module will be undefined. Similarly, if Sleep
occurs in the middle of a master reception, the module behavior will also be undefined. The
transmitter and receiver will stop at Sleep when in Master mode. Register contents are not
affected by going into Sleep mode or coming out of Sleep mode; there is no automatic way to
prevent Sleep entry if a transmission or reception is pending. The user software must
synchronize Sleep entry with I
2
C operation to avoid undefined module behavior.
9.3 When the Device Enters Idle Mode
When the device executes a PWRSAV 1 instruction, the device enters Idle mode. The module
enters a power-saving state in Idle mode, depending on the I2CSIDL bit (I2CxCON<13> or
I2CxCONL<13>). If I2CSIDL = 1, the module enters the Power-Saving mode, similar to actions
while entering Sleep mode. If I2CSIDL = 0, the module does not enter a Power-Saving mode and
continues to operate normally.
10.0 PERIPHERAL MODULE DISABLE (PMD X) REGISTERS
The Peripheral Module Disable (PMDx) registers provide a method to disable the I
2
C modules
by stopping all clock sources supplied to that module. When a peripheral is disabled through the
appropriate PMDx control bit, the peripheral is in a minimum power consumption state. The
control and status registers associated with the peripheral are also disabled, so writes to those
registers will have no effect and read values will be invalid. A peripheral module is only enabled
if the I2CxMD bit in the PMDx register is cleared.
11.0 EFFECTS OF A RESET
A Reset disables the I
2
C module and terminates any active or pending message activity. Refer
to the I2Cx Control (I2CxCON or I2CxCONH and I2CxCONL) and I2Cx Status (I2CxSTAT)
register definitions (Register 3-1, Register 3-2, Register 3-3 and Register 3-4) for the Reset
conditions of those registers.
Note: As per the slave I
2
C behavior, a slave interrupt is generated only on an address
match. Therefore, when an I
2
C slave is in Sleep mode and it receives a message
from the master, the clock required to match the received address is derived from
the master. Only on an address match, will the interrupt be generated and the
device can wake-up from Sleep, provided the interrupt has been enabled and an
ISR has been defined.
Note 1: The I2CxCON or I2CxCONL and I2CxCONH are not available on all devices. Refer
to the specific device data sheet for availability.
2: In this discussion, ‘Idle’ refers to the CPU power-saving state. The lower case ‘idle’
refers to the time when the I
2
C module is not transferring data on the bus.

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