# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Family Data Sheet

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© 2011-2012 Microchip Technology Inc. Preliminary DS39997C-page 283
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
TABLE 26-33: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING
REQUIREMENTS FOR PIC24FJ16MC101/102
AC CHARACTERISTICS
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ T A ≤ +85°C for Industrial
-40°C ≤ T A ≤ +125°C for Extended
Param
No.
Symbol Characteristic
(1)
Min Typ
(2)
Max Units Conditions
SP70 TscP Maximum SCK Input Frequency — — 15 MHz
See Note 3
SP72 TscF SCKx Input Fall Time — — — ns See parameter DO32
and Note 4
SP73 TscR SCKx Input Rise Time — — — ns See parameter DO31
and Note 4
SP30 TdoF SDOx Data Output Fall Time — — — ns See parameter DO32
and Note 4
SP31 TdoR SDOx Data Output Rise Time — — — ns See parameter DO31
and Note 4
SP35 TscH2doV,
TscL2doV
SDOx Data Output Valid after
SCKx Edge
— 6 20 ns —
SP36 TdoV2scH,
TdoV2scL
SDOx Data Output Setup to
First SCKx Edge
30 — — ns —
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30 — — ns —
SP41 TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30 — — ns —
SP50 TssL2scH,
TssL2scL
SSx
↓ to SCKx ↑ or SCKx Input 120 — — ns —
SP51 TssH2doZ SSx
↑ to SDOx Output
High-Impedance
(4)
10 — 50 ns —
SP52 TscH2ssH
TscL2ssH
SSx
after SCKx Edge 1.5 T CY + 40 — — ns
See Note 4
SP60 TssL2doV SDOx Data Output Valid after
SSx Edge
— — 50 ns —
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCK clock generated by the Master must
not violate this specification.
4: Assumes 50 pF load on all SPIx pins.

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