# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 -- UART

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 2009-2013 Microchip Technology Inc. DS70000582E-page 39
UART
13.2.5 CLOCK JITTER
Due to jitter or slight frequency differences between devices, it is possible for the next falling bit
edge to be missed for one of the 16x periods. In that case, a one clock wide pulse appears on
the decoded data stream. Since the UART performs a Majority Detect around the bit center, this
does not cause erroneous data (see Figure 13-6 for details).
Figure 13-6: Clock Jitter Causing a Pulse Between Consecutive Zeros
16 Periods 16 Periods
Extra Pulse will be Ignored
UxRX (rx_in)
Decoded Data

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