# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004

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 2010-2013 Microchip Technology Inc. DS39881E-page 109
PIC24FJ64GA004 FAMILY
10.4.3.2 Output Mapping
In contrast to inputs, the outputs of the Peripheral Pin
Select options are mapped on the basis of the pin. In
this case, a control register associated with a particular
pin dictates the peripheral output to be mapped. The
RPORx registers are used to control output mapping.
Like the RPINRx registers, each register contains two
5-bit fields; each field being associated with one RPn
pin (see Register 10-15 through Register 10-27). The
value of the bit field corresponds to one of the periph-
erals and that peripherals output is mapped to the pin
(see Table 10-3).
Because of the mapping technique, the list of peripher-
als for output mapping also includes a null value of
00000. This permits any given pin to remain discon-
nected from the output of any of the pin-selectable
peripherals.
TABLE 10-3: SELECTABLE OUTPUT
SOURCES (MAPS FUNCTION
TO OUTPUT)
10.4.3.3 Mapping Limitations
The control schema of the Peripheral Pin Select is
extremely flexible. Other than systematic blocks that
prevent signal contention, caused by two physical pins
being configured as the same functional input or two
functional outputs configured as the same pin, there
are no hardware enforced lockouts. The flexibility
extends to the point of allowing a single input to drive
multiple peripherals or a single functional output to
drive multiple output pins.
10.4.4 CONTROLLING CONFIGURATION
CHANGES
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. PIC24F devices include three features to
prevent alterations to the peripheral map:
 Control register lock sequence
 Continuous state monitoring
 Configuration bit remapping lock
10.4.4.1 Control Register Lock
Under normal operation, writes to the RPINRx and
RPORx registers are not allowed. Attempted writes will
appear to execute normally, but the contents of the
registers will remain unchanged. To change these reg-
isters, they must be unlocked in hardware. The register
lock is controlled by the IOLOCK bit (OSCCON<6>).
Setting IOLOCK prevents writes to the control
registers; clearing IOLOCK allows writes.
To set or clear IOLOCK, a specific command sequence
must be executed:
1. Write 46h to OSCCON<7:0>.
2. Write 57h to OSCCON<7:0>.
3. Clear (or set) IOLOCK as a single operation.
Unlike the similar sequence with the oscillators LOCK
bit, IOLOCK remains in one state until changed. This
allows all of the Peripheral Pin Selects to be configured
with a single unlock sequence, followed by an update
to all control registers, then locked with a second lock
sequence.
10.4.4.2 Continuous State Monitoring
In addition to being protected from direct writes, the
contents of the RPINRx and RPORx registers are
constantly monitored in hardware by shadow registers.
If an unexpected change in any of the registers occurs
(such as cell disturbances caused by ESD or other
external events), a Configuration Mismatch Reset will
be triggered.
Function
Output Function
Number
(1)
Output Name
NULL
(2)
0 NULL
C1OUT 1 Comparator 1 Output
C2OUT 2 Comparator 2 Output
U1TX 3 UART1 Transmit
U1RTS
(3)
4 UART1 Request-to-Send
U2TX 5 UART2 Transmit
U2RTS
(3)
6 UART2 Request-to-Send
SDO1 7 SPI1 Data Output
SCK1OUT 8 SPI1 Clock Output
SS1OUT 9 SPI1 Slave Select Output
SDO2 10 SPI2 Data Output
SCK2OUT 11 SPI2 Clock Output
SS2OUT 12 SPI2 Slave Select Output
OC1 18 Output Compare 1
OC2 19 Output Compare 2
OC3 20 Output Compare 3
OC4 21 Output Compare 4
OC5 22 Output Compare 5
Note 1: Value assigned to the RPn<4:0> pins corre-
sponds to the peripheral output function
number.
2: The NULL function is assigned to all RPn
outputs at device Reset and disables the
RPn output function.
3: IrDA
®
BCLK functionality uses this output.

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