# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- CPU

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Section 2. CPU
© 2006 Microchip Technology Inc. Advance Information DS39703A-page 2-25
CPU
2
2.12 REGISTER MAPS
A summary of the registers associated with the PIC24F CPU core is provided in Table 2-5.
Table 2-5: Core SFR Memory Map (User Mode)
Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
W0 Working Register 0 0000
W1 Working Register 1 0000
W2 Working Register 2 0000
W3 Working Register 3 0000
W4 Working Register 4 0000
W5 Working Register 5 0000
W6 Working Register 6 0000
W7 Working Register 7 0000
W8 Working Register 8 0000
W9 Working Register 9 0000
W10 Working Register 10 0000
W11 Working Register 11 0000
W12 Working Register 12 0000
W13 Working Register 13 0000
W14 Working Register 14 0000
W15 Working Register 15 0800
SPLIM Stack Pointer Limit xxxx
PCL Program Counter, Low Word 0000
PCH
— — — — — — — — Program Counter, High Byte 0000
TBLPAG
— — — — — — — — Table Page Addess Pointer 0000
PSVPAG
— — — — — — — — Program Memory Visibility Page Address Pointer 0000
RCOUNT Repeat Loop Counter xxxx
SR
— — — — — — — DC IPL2 IPL1 IPL0 RA N OV Z C 0000
CORCON
— — — — — — — — — — — — IPL3 PSV — — 0000
DISICNT
— — Disable Interrupts Counter xxxx
Legend: x = unknown value on Reset, — = unimplemented, read as '0’. Reset values are shown in hexidecimal.
Note 1: Refer to the device data sheet for specific core register map details.

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