# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Motor Control PWM

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PIC24F Family Reference Manual
DS39735A-page 47-20 Preliminary © 2010 Microchip Technology Inc.
47.6 MCPWM MODULE OPERATING MODES
The MCPWM module can be configured for one of four modes of operation using the PWM
Time Base Mode Select (PTMOD) control bits in the PWM Time Base Control (PxTCON<1:0>)
register. The four operating modes are described in the following four sections.
47.6.1 Free-Running Mode (PTMOD<1:0> = 0b00)
In this mode, the PWM Time Base (PxTMR) register will count upward until the value in the
PWM Time Base Period (PxTPER) register is matched. The PxTMR register is reset on the
following input clock edge. The timer will continue counting upward and resetting as long as
the PWM Time Base Timer Enable (PTEN) bit in the PWM Time Base Control (PxTCON<15>)
register remains set.
47.6.2 Single Event Mode (PTMOD<1:0> = 0b01)
The PWM timer (PxTMR) will begin counting upward when the PTEN bit is set. When the
PxTMR value matches the PxTPER register value, the PxTMR register is reset on the following
input clock edge and the PTEN bit is cleared by the hardware to halt the timer.
47.6.3 Continuous Up/Down Count Mode (PTMOD<1:0> = 0b10)
In this mode, the PWM timer (PxTMR) will count upward until the value in the PxTPER register
is matched. The timer will start counting downward on the following clock edge and continue
counting down until it reaches zero. The PWM Time Base Count Direction Status (PTDIR) bit in
the PWM Time Base (PxTMR<15>) register indicates the counting direction. This bit is set
when the timer starts counting downward.
47.6.4 Continuous Up/Down Count Mode with Interrupts for Double
Update of Duty Cycle (PTMOD<1:0> = 0b11)
This mode is similar to the Continuous Up/Down Count mode, with the exception that an
interrupt event is generated twice per time base: once when the PxTMR register is equal to
zero and a second time when a period match occurs.

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