# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Family Data Sheet

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© 2011-2012 Microchip Technology Inc. Preliminary DS39997C-page 67
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
6.2 POR
A POR circuit ensures the device is reset from power-
on. The POR circuit is active until VDD crosses the
V
POR threshold and the delay TPOR has elapsed. The
delay TPOR ensures the internal device bias circuits
become stable.
The device supply voltage characteristics must meet
the specified starting voltage and rise rate require-
ments to generate the POR. Refer to Section 26.0
“Electrical Characteristics” for details.
The POR status bit (POR) in the Reset Control register
(RCON<0>) is set to indicate the Power-on Reset.
6.3 BOR and PWRT
The on-chip regulator has a BOR circuit that resets the
device when the VDD is too low (V DD < VBOR) for proper
device operation. The BOR circuit keeps the device in
Reset until V
DD crosses the VBOR threshold and the
delay TBOR has elapsed. The delay TBOR ensures the
voltage regulator output becomes stable.
The BOR status bit (BOR) in the Reset Control register
(RCON<1>) is set to indicate the Brown-out Reset.
The device will not run at full speed after a BOR as the
V
DD should rise to acceptable levels for full-speed
operation. The PWRT provides power-up time delay
(T
PWRT) to ensure that the system power supplies have
stabilized at the appropriate levels for full-speed oper-
ation before the SYSRST
is released.
Refer to Section 23.0 “Special Features” for further
details.
Figure 6-3 shows the typical brown-out scenarios. The
Reset delay (T
BOR + TPWRT) is initiated each time VDD
rises above the VBOR trip point.
FIGURE 6-3: BROWN-OUT SITUATIONS
VDD
SYSRST
VBOR
V
DD
SYSRST
VBOR
V
DD
SYSRST
VBOR
T
BOR + TPWRT
VDD dips before PWRT expires
T
BOR + TPWRT
TBOR + TPWRT

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