# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

- 1
- 2
…
- 164
- 165
- 166
- 167
- 168
…
- 501
- 502

16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 166 © 2005-2011 Microchip Technology Inc.
BTSS
Bit Test Ws, Skip if Set
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} BTSS Ws, #bit4
[Ws],
[Ws++],
[Ws--],
[++Ws],
[--Ws],
Operands: Ws ∈ [W0 ... W15]
bit4 ∈ [0 ... 15]
Operation: Test (Ws)<bit4>, skip if set.
Status Affected: None
Encoding: 1010 0110 bbbb 0000 0ppp ssss
Description: Bit ‘bit4’ in Ws is tested. If the tested bit is ‘1’, the next instruction (fetched
during the current instruction execution) is discarded and on the next
cycle, a NOP is executed instead. If the tested bit is ‘0’, the next instruction
is executed as normal. In either case, the contents of Ws are not changed.
For the bit4 operand, bit numbering begins with the Least Significant bit
(bit 0) and advances to the Most Significant bit (bit 15) of the word. Either
register direct or indirect addressing may be used for Ws.
The ‘b’ bits select the value bit4, the bit position to test.
The ‘s’ bits select the source register.
The ‘p’ bits select the source Address mode.
Note: This instruction operates in Word mode only.
Words: 1
Cycles:
1 (2 or 3 if the next instruction is skipped)
(1)
Note 1:
In dsPIC33E and PIC24E devices, the listed cycle count does not apply to read and
read-modify-write operations on non-CPU Special Function Registers. For more
details, see
Note 3
in
Section 3.2.1 “Multi-Cycle Instructions”
.
Example 1:
002000 HERE: BTSS W0, #0x0
002002 GOTO BYPASS
002004 . . .
002006 . . .
002008 BYPASS: . . .
00200A . . .
; If bit 0 of W0 is 1,
; skip the GOTO
Before
Instruction
After
Instruction
PC 00 2000 PC 00 2006
W0 264F W0 264F
SR 0000 SR 0000

- 1
- 2
…
- 164
- 165
- 166
- 167
- 168
…
- 501
- 502