# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Serial Peripheral Interface

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PIC24F Family Reference Manual
DS39699B-page 23-9 Advance Information © 2007 Microchip Technology Inc.
23.3 MODES OF OPERATION
The SPIx module has flexible operating modes which are discussed in the following subsections:
• 8-Bit and 16-Bit Data Transmission/Reception
• Master and Slave Modes
• Framed SPI Modes
23.3.1 8-Bit vs. 16-Bit Operation
The MODE16 control bit (SPIxCON1<10>) allows the module to communicate in either 8-bit or
16-bit modes. The functionality will be the same for each mode, except for the number of bits that
are received and transmitted. Additionally, the following should be noted in this context:
The module is reset when the value of the MODE16 bit is changed. Consequently, the bit should
not be changed during normal operation.
Data is transmitted out of bit 7 of the SPIxSR for 8-bit operation, while it is transmitted out of bit 15
of the SPIxSR for 16-bit operation. In both modes, data is shifted into bit 0 of the SPIxSR.
When transmitting or receiving data, 8 clock pulses at the SCKx pin are required to shift in/out
data in 8-bit mode, while 16 clock pulses are required in 16-bit mode.
23.3.2 Master and Slave Modes
In Standard (legacy) Master and Slave modes, data can be thought of as taking a direct path
between the Most Significant bit of one module’s shift register and the Least Significant bit of the
other, and then into the appropriate Transmit or Receive Buffer. The module configured as the
master module provides the serial clock and synchronization signals (as required) to the slave
device. The relationship between the master and slave modules is shown in Figure 23-3.
Figure 23-3: SPIx Master/Slave Connection
Serial Receive Buffer
(SPIxRXB)
Shift Register
(SPIxSR)
LSb
MSb
SDIx
SDOx
PROCESSOR 2 (SPIx Slave)
SCKx
SSx
(1)
Serial Transmit Buffer
(SPIxTXB)
Serial Receive Buffer
(SPIxRXB)
Shift Register
(SPIxSR)
MSb
LSb
SDOx
SDIx
PROCESSOR 1 (SPIx Master)
Serial Clock
SSEN (SPIxCON1<7>) = 1 and MSTEN (SPIxCON1<5>) = 0
Note 1: Using the SSx pin in Slave mode of operation is optional.
2: User must write transmit data to/read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are
memory mapped to SPIxBUF.
SSx
SCKx
Serial Transmit Buffer
(SPIxTXB)
MSTEN (SPIxCON1<5>) = 1
SPIx Buffer
(SPIxBUF)
(2)
SPIx Buffer
(SPIxBUF)
(2)

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