# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Serial Peripheral Interface

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© 2007 Microchip Technology Inc. Advance Information DS39699B-page 23-12
Section 23. Serial Peripheral Interface (SPI)
Serial Peripheral
Interface (SPI)
23
23.3.2.2 SLAVE MODE
In Slave mode, data is transmitted and received as the external clock pulses appear on the SCKx
pin. The CKP (SPIxCON<6>) and CKE (SPIxCON<8>) bits determine on which edge of the clock
data transmission occurs. Both data to be transmitted and data that is received are respectively
written into or read from the SPIxBUF register. The rest of the operation of the module is identical
to that in the Master mode.
To set up the SPIx module for the Standard Slave mode of operation:
1. Clear the SPIxBUF register.
2. If using interrupts:
• Clear the SPIxIF bit in the respective IFSn register.
• Set the SPIxIE bit in the respective IECn register.
• Write the SPIxIP bits in the respective IPCn register to set the interrupt priority.
3. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with MSTEN
(SPIxCON1<5>) = 0.
4. Clear the SMP bit.
5. If the CKE bit is set, then the SSEN bit (SPIxCON1<7>) must be set to enable the SSx
pin.
6. Clear the SPIROV bit (SPIxSTAT<6>).
7. Enable SPIx operation by setting the SPIEN bit (SPIxSTAT<15>).
23.3.2.2.1 Slave Select Synchronization
The SSx
pin allows a Synchronous Slave mode. If the SSEN (SPIxCON1<7>) bit is set, trans-
mission and reception are enabled in Slave mode only if the SSx
pin is driven to a low state (see
Figure 23-6). The port output or other peripheral outputs must not be driven in order to allow the
SSx pin to function as an input. If the SSEN bit is set and the SSx pin is driven high, the SDOx
pin is no longer driven and will tri-state even if the module is in the middle of a transmission. An
aborted transmission will be retried the next time the SSx
pin is driven low, using the data held
in the SPIxTXB register. If the SSEN bit is not set, the SSx
pin does not affect the module
operation in Slave mode.
23.3.2.2.2 SPIxTBF Status Flag Operation
The function of the SPIxTBF (SPIxSTAT<1>) bit is different in the Slave mode of operation.
If SSEN (SPIxCON1<7>) is cleared, the SPIxTBF is set when the SPIxBUF is loaded by the user
code. It is cleared when the module transfers SPIxTXB to SPIxSR. This is similar to the SPIxTBF
bit function in Master mode.
If SSEN is set, the SPIxTBF is set when the SPIxBUF is loaded by the user code. However, it is
cleared only when the SPIx module completes data transmission. A transmission will be aborted
when the SSx
pin goes high and may be retried at a later time. Each data word is held in SPIxTXB
until all bits are transmitted to the receiver.
Note: To meet module timing requirements, the SSx pin must be enabled in Slave mode
when CKE = 1 (refer to Figure 23-7 for details).

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