# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Programming and Diagnostics

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PIC24F Family Reference Manual
DS39716A-page 33-10 Advance Information © 2006 Microchip Technology Inc.
33.4.5 Boundary Scan Testing (BST)
Boundary Scan Testing (BST) is the method of controlling and observing the boundary pins of
the JTAG compliant device, like those of the PIC24F family, utilizing software control. BST can
be used to test connectivity between devices by daisy-chaining JTAG compliant devices to form
a single scan chain. Several scan chains can exist on a PCB to form multiple scan chains. These
multiple scan chains can then be driven simultaneously to test many components in parallel.
Scan chains can contain both JTAG compliant devices and non-JTAG compliant devices.
A key advantage of BST is that it can be implemented without physical test probes; all that is
needed is a 4-wire or 5-wire interface and an appropriate test platform. Since JTAG boundary
scan has been available for many years, many software tools exist for testing scan chains without
the need for extensive physical probing. The main drawback to BST is that it can only evaluate
digital signals and circuit continuity; it cannot measure input or output voltage levels or currents.
33.4.5.1 RELATED JTAG FILES
To implement BST, all JTAG test tools will require a Boundary Scan Description Language
(BSDL) file. BSDL is a subset of VHDL (VHSIC Hardware Description Language), and is
described as part of IEEE Std. 1149.1. The device-specific BSDL file describes how the standard
is implemented on a particular device and how it operates.
The BSDL file for a particular device includes the following:
• The pinout and package configuration for the particular device
• The physical location of the TAP pins
• The Device ID register and the device ID
• The length of the Instruction Register
• The supported BST instructions and their binary codes
• The length and structure of the Boundary Scan register
• The boundary scan cell definition
Device-specific BSDL files are available at Microchip’s web site, www.microchip.com. The name
for each BSDL file is the device name and silicon revision. For example,
PIC24FJ128GA010_A2.BSD, is the BSDL file for the PIC24FJ128GA010, silicon revision A2.
33.4.6 JTAG Device Programming
The JTAG interface can also be used to program PIC24F family devices in their target applications.
Using the JTAG interface allows application designers to include a dedicated test and programming
port into their applications, with a single 4-pin interface, without imposing the circuit constraints that
the ICSP interface may require.
JTAG device programming actually uses the standard ICSP method over the four pins of the TAP
interface. When triggered by the appropriate JTAG command sequence, the TDI, TDO and TCK
pins assume the functions of the PGD and PGC pins. Aside from this pin remapping, ICSP
programming over the JTAG interface behaves exactly as it does over the standard ICSP
interface.
Because of the added time overhead for switching the TAP interface, JTAG device programming
takes slightly longer than standard ICSP programming over the PGC and PGD pins. Enhanced
ICSP programming is not available with JTAG programming.

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