# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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 2007-2014 Microchip Technology Inc. DS70000195F-page 67
Inter-Integrated Circuit™ (I
2
C™)
14.0 DESIGN TIPS
Question 1: I am operating as a bus master and transmitting data. Why do slave and
receive interrupts keep occurring at the same time?
Answer: The master and slave circuits are independent. The slave will receive events from
the bus sent by the master.
Question 2: I am operating as a slave and I write data to the I2CxTRN register. Why is
the data not being transmitted?
Answer: The slave enters an automatic Wait when preparing to transmit. Ensure that you
set the SCLREL bit to release the I
2
C clock.
Question 3: How do I tell what state the master module is in?
Answer: Looking at the condition of the SEN, RSEN, PEN, RCEN, ACKEN and TRSTAT
bits will indicate the state of the master module. If all bits are ‘0’, the module is
Idle.
Question 4: Operating as a slave, I receive a byte while STREN = 0. What should the
user software do if it cannot process the byte before the next one is
received?
Answer: Because STREN was ‘0’, the module did not generate an automatic Wait on the
received byte. However, the user software may, at any time during the message,
set STREN and then clear SCLREL. This will cause a Wait on the next
opportunity to synchronize the SCLx clock.
Question 5: My I
2
C system is a multi-master system. Why are my messages being
corrupted when I attempt to send them?
Answer: In a multi-master system, other masters may cause bus collisions. In the ISR for
the master, check the BCL status bit to ensure that the operation completed
without a collision. If a collision is detected, the message must be re-sent from
the beginning.
Question 6: My I
2
C system is a multi-master system. How can I tell when it is okay to
begin a message?
Answer: Check the S status bit. If S = 0, the bus is Idle.
Question 7: I tried to send a Start condition on the bus, then transmit a byte by writing
to the I2CxTRN register. The byte did not get transmitted. Why?
Answer: You must wait for each event on the I
2
C bus to complete before starting the next
one. In this case, you should poll the SEN bit to determine when the Start event
completed or wait for the master I
2
C interrupt before data is written to the
I2CxTRN register.
Note: In some devices, a separate bus collision interrupt (I2CxBCIF) is generated instead
of a master event interrupt (MI2CxIF).

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