# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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 2007-2014 Microchip Technology Inc. DS70000195F-page 57
Inter-Integrated Circuit™ (I
2
C™)
7.5.2 EXAMPLE MESSAGES OF SLAVE TRANSMISSION
The slave transmissions for 7-bit address messages are illustrated in Figure 7-15. When the
address matches and the R/W
status bit of the address indicates a slave transmission, the
module automatically initiates clock stretching by clearing the SCLREL bit and generates an
interrupt to indicate a response byte is required. The user software writes the response byte into
the I2CxTRN register. As the transmission completes, the master responds with an ACK
. If the
master replies with an ACK
, the master expects more data, and the module again clears the
SCLREL bit and generates another interrupt. If the master responds with a NACK, no more data
is required and the module will not stretch the clock, but will generate an interrupt.
The slave transmissions for 10-bit address messages require the slave to first recognize a 10-bit
address. Because the master must send two bytes for the address, the R/W
status bit in the first
byte of the address specifies a write. To change the message to a read, the master sends a
Repeated Start and repeats the first byte of the address with the R/W
status bit specifying a read.
At this point, the slave transmission begins as illustrated in Figure 7-16.

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