# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Family Data Sheet

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© 2011-2012 Microchip Technology Inc. Preliminary DS39997C-page 139
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
11.0 TIMER1
The Timer1 module is a 16-bit timer, which can serve
as the time counter for the real-time clock, or operate
as a free-running interval timer/counter. Timer1 can
operate in three modes:
• 16-bit Timer
• 16-bit Synchronous Counter
• 16-bit Asynchronous Counter
Timer1 also supports these features:
• Timer gate operation
• Selectable prescaler settings
• Timer operation during CPU Idle and Sleep
modes
• Interrupt on 16-bit Period register match or falling
edge of external gate signal
Figure 11-1 presents a block diagram of the 16-bit timer
module.
To configure Timer1 for operation:
1. Load the timer value into the TMR1 register.
2. Load the timer period value into the PR1
register.
3. Select the timer prescaler ratio using the
TCKPS<1:0> bits in the T1CON register.
4. Set the Clock and Gating modes using the TCS
and TGATE bits in the T1CON register.
5. Set or clear the TSYNC bit in T1CON to select
synchronous or asynchronous operation.
6. If interrupts are required, set the interrupt enable
bit, T1IE. Use the priority bits, T1IP<2:0>, to set
the interrupt priority.
7. Set the TON bit (= 1) in the T1CON register.
FIGURE 11-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM
Note 1: This data sheet summarizes the features
of the PIC24FJ16MC101/102 and
PIC24FJ32MC101/102/104 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 14. “Timers”
(DS39704) in the “PIC24F Family
Reference Manual”, which is available
from the Microchip web site
(www.microchip.com).
2: It is important to note that the
specifications in Section 26.0 “Electri-
cal Characteristics” of this data sheet,
supercede any specifications that may be
provided in PIC24F Family Reference
Manual sections.
3: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
TON
SOSCI
SOSCO/
PR1
Set T1IF
Equal
Comparator
TMR1
Reset
SOSCEN
1
0
TSYNC
Q
Q D
CK
TCKPS<1:0>
Prescaler
1, 8, 64, 256
2
TGATE
T
CY
1
0
T1CK
TCS
1x
01
TGATE
00
Sync
Gate
Sync

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