# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 -- UART

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dsPIC33/PIC24 Family Reference Manual
DS70000582E-page 44  2009-2013 Microchip Technology Inc.
15.1.3 ERROR DETECTION
The transmitter is responsible for calculating the parity bit value. Parity is always even, defined
as the number of logic ones and the parity bit, always being an even count. The receiver also
calculates the parity value and compares it to the received parity bit. If a discrepancy is found,
the error is flagged by the receiver, pulling the line low for a duration defined by T0PD
(UxSCCON<2>).
The transmitter tests the I/O line at Time 11 ± 0.2 ETU after the leading edge of the Start bit of a
character was sent. If the transmitter detects an error by detecting the state low on the I/O line,
it will repeat the disputed character after a delay of at least 2 ETU, following the detection of the
error. The number of repeats is configured with the TXRPT<1:0> bits (UxSCCON<5:4>). See
Figure 15-4 for timing details in T = 0 mode.
Figure 15-4: T = 0 Character Repetition Timing
Note: Protocol characteristics, electrical characteristics of the Smart Card, Answer-To-
Reset (ATR), PPS (Protocol Parameter Selection), calculation of guard time and
wait times are out of scope of this FRM. Please refer to the licensed version of the
ISO 7816-3 document for details about Smart Card communication.
Bit Clock
0 ETU
10.0 ± 0.2 ETU
(2)
10.5 ± 0.2 ETU
(3)
11.0 ± 0.2 ETU
(4)
I/O
Start Bit
Bit 0 Bit 1
(1)
Parity
Note 1: 8-bit character.
2: At 10.0 ± 0.2 ETU, the transmitter disables the driver.
3: At 10.5 ± 0.2 ETU, the receiver sets the I/O line low if a parity error is detected.
4: At 11.0 ± 0.2 ETU, the transmitter tests the I/O line.
5: See T0PD (UxSCCON<2>) in Register 15-1.
Character 1
(5)

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