# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Programming and Diagnostics

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PIC24F Family Reference Manual
DS39716A-page 33-4 Advance Information © 2006 Microchip Technology Inc.
33.4 JTAG BOUNDARY SCAN
As the complexity and density of board designs increases, testing electrical connections between
the components on fully assembled circuit boards poses many challenges. To address these
challenges, the Joint Test Action Group (JTAG) developed a method for boundary scan testing that
was later standardized as IEEE 1149.1-2001,
“IEEE Standard Test Access Port and Boundary
Scan Architecture”
. Since its adoption, many microcontroller manufacturers have added device
programming to the capabilities of the test port.
The JTAG boundary scan method is the process of adding a Shift register stage adjacent to each
of the component’s I/O pins. This permits signals at the component boundaries to be controlled
and observed, using a defined set of scan test principles. An external tester or controller provides
instructions and reads the results in a serial fashion. The external device also provides common
clock and control signals. Depending on the implementation, access to all test signals is provided
through a standardized 4-pin or 5-pin interface.
In system-level applications, individual JTAG enabled components are connected through their
individual testing interfaces (in addition to their more standard application-specific connections).
Devices are connected in a series or daisy-chained fashion, with the test output of one device
connected exclusively to the test input of the next device in the chain. Instructions in the JTAG
boundary scan protocol allow the testing of any one device in the chain, or any combination of
devices, without testing the entire chain. In this method, connections between components, as
well as connections at the boundary of the application, may be tested.
A typical application incorporating the JTAG boundary scan interface is shown in Figure 33-1. In
this example, a PIC24F microcontroller is daisy-chained to a second JTAG compliant device.
Note that the TDI line from the external tester supplies data to the TDI pin of the first device in
the chain (in this case, the microcontroller). The resulting test data for this two-device chain is
provided from the TDO pin of the second device to the TDO line of the tester.
This section describes the JTAG module and its general use. Users interested in using the JTAG
interface for device programming should refer to the appropriate PIC24F device programming
specification for more information.
Figure 33-1: Overview of PIC24F-Based JTAG Compliant Application Showing Daisy-Chaining of Components
TDI
TDO
TCK
TMS
TDI
TDO
TCK
TMS
TDI
TDO
TCK
TMS
JTAG
Controller
PIC24F
PIC24F
(or other
JTAG compliant
device)
TRST
PIC24F-Based Application
Standard
JTAG Connector
(optional)

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