# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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© 2005-2011 Microchip Technology Inc. DS70157F-page 83
Section 4. Instruction Set Details
Instruction Set
Details
4
4.12 ACCUMULATOR USAGE (dsPIC30F, dsPIC33F AND dsPIC33E DEVICES)
Accumulators A and B are utilized by DSP instructions to perform mathematical and shifting
operations. Since the accumulators are 40 bits wide and the X and Y data paths are only 16 bits,
the method to load and store the accumulators must be understood.
Item A in Figure 4-14 shows that each 40-bit Accumulator (ACCA and ACCB) consists of an 8-bit
Upper register (ACCxU), a 16-bit High register (ACCxH) and a 16-bit Low register (ACCxL). To
address the bus alignment requirement and provide the ability for 1.31 math, ACCxH is used as
a destination register for loading the accumulator (with the LAC instruction), and also as a source
register for storing the accumulator (with the SAC.R instruction). This is represented by Item B,
Figure 4-14, where the upper and lower portions of the accumulator are shaded. In reality, during
accumulator loads, ACCxL is zero backfilled and ACCxU is sign-extended to represent the sign
of the value loaded in ACCxH.
When Normal (31-bit) Saturation is enabled, DSP operations (such as ADD, MAC, MSC, etc.)
utilize solely ACCxH:ACCxL (Item C in
Figure 4-14) and ACCxU is only used to maintain the sign
of the value stored in ACCxH:ACCxL. For instance, when a MPY instruction is executed, the
result is stored in ACCxH:ACCxL, and the sign of the result is extended through ACCxU.
When Super Saturation is enabled, or when saturation is disabled, all registers of the
accumulator may be used (Item D in
Figure 4-14) and the results of DSP operations are stored
in ACCxU:ACCxH:ACCxL. The benefit of ACCxU is that it increases the dynamic range of the
accumulator, as described in Section 4.11.1 “Integer and Fractional Data”. Refer to Table 4-10
to see the range of values which may be stored in the accumulator when in Normal and Super
Saturation modes.
Figure 4-14: Accumulator Alignment and Usage
A)
D)
C)
B)
ACCxU
ACCxH
ACCxL
A) 40-bit Accumulator consists of ACCxU:ACCxH:ACCxL
B) Load and Store operations
C) Operations in Normal Saturation mode
D) Operations in Super Saturation mode or with saturation disabled
31.30
Implied Radix Point (between bits 31 and 30)
0
15
16
32
39

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