# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 218 © 2005-2011 Microchip Technology Inc.
DEC
Decrement Ws
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} DEC{.B} Ws, Wd
[Ws], [Wd]
[Ws++], [Wd++]
[Ws--], [Wd--]
[++Ws], [++Wd]
[--Ws], [--Wd]
Operands: Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]
Operation: (Ws) – 1 →Wd
Status Affected: DC, N, OV, Z, C
Encoding: 1110 1001 0Bqq qddd dppp ssss
Description: Subtract one from the contents of the source register Ws and place the
result in the destination register Wd. Either register direct or indirect
addressing may be used by Ws and Wd.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
Words: 1
Cycles:
1
(1)
Note 1:
In dsPIC33E and PIC24E devices, the listed cycle count does not apply to read and
read-modify-write operations on non-CPU Special Function Registers. For more
details, see
Note 3
in
Section 3.2.1 “Multi-Cycle Instructions”
.
Example 1:
DEC.B [W7++], [W8++] ; DEC [W7] and store to [W8] (Byte mode)
; Post-increment W7, W8
Before
Instruction
After
Instruction
W7 2301 W7 2302
W8 2400 W8 2401
Data 2300 5607 Data 2300 5607
Data 2400 ABCD Data 2400 AB55
SR 0000 SR 0000

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