# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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 2007-2014 Microchip Technology Inc. DS70000195F-page 13
Inter-Integrated Circuit™ (I
2
C™)
Register 3-3: I2CxCONH: I2Cx Control Register High
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as ‘0’
bit 6 PCIE: Stop Condition Interrupt Enable bit (I
2
C™ Slave mode only)
1 = Enables the interrupt on detection of a Stop condition
0 = Stop detection interrupts are disabled
bit 5 SCIE: Start Condition Interrupt Enable bit (I
2
C Slave mode only)
1 = Enables the interrupt on detection of a Start or Restart condition
0 = Start detection interrupts are disabled
bit 4 BOEN: Buffer Overwrite Enable bit (I
2
C Slave mode only)
1 = The I2CxRCV register is updated and an ACK
is generated for a received address or data byte,
ignoring the state of the I2COV bit only if the RBF bit = 0
0 = The I2CxRCV register is only updated when the I2COV bit is clear
bit 3 SDAHT: SDAx Hold Time Selection bit
1 = Minimum of 300 ns hold time on SDAx after the falling edge of the SCLx clock
0 = Minimum of 100 ns hold time on SDAx after the falling edge the of SCLx clock
bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I
2
C Slave mode only)
If, on the rising edge of the SCLx, SDAx is sampled low when the module is outputting a high state, the
BCL bit is set and the bus goes into Idle mode. This Detection mode is valid only during the data and
ACK transmit sequences.
1 = Enables the slave bus collision interrupts
0 = Disables the slave bus collision interrupts
bit 1 AHEN: Address Hold Enable bit (I
2
C Slave mode only)
1 = Following the falling edge of the eighth SCLx clock for a matching received address byte; the
SCLREL bit (I2CxCONL<12>) will be cleared and the SCLx will be held low
0 = Address holding is disabled
bit 0 DHEN: Data Hold Enable bit (I
2
C Slave mode only)
1 = Following the eighth falling edge of the SCLx clock for a received data byte; slave hardware clears
the SCLREL bit (I2CxCONL<12>) and SCLx is held low
0 = Data holding is disabled

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