# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Interrupts

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© 2006 Microchip Technology Inc. Advance Information DS39707A-page 8-19
Section 8. Interrupts
Interrupts
8
Register 8-10: IPCn: Interrupt Priority Register 29 (Interrupt Vectors116 and 117)
(1)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— V117IP2 V117IP1 V117IP0 — V116IP2 V116IP1 V116IP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at any Reset ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as ‘0’
bit 6-4 V117IP2:V117IP0: Interrupt Priority bits for Interrupt Vector 117
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3 Unimplemented: Read as ‘0’
bit 2-0 V116IP2:V116IP0: Interrupt Priority bits for Interrupt Vector 116
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
Note 1: Not all interrupt vectors are implemented on all devices. Refer to the Interrupt Vector Table for the specific
device or family data sheet to verify where interrupt vectors are implemented for a specific device.

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