# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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dsPIC33/PIC24 Family Reference Manual
DS70000195F-page 46  2007-2014 Microchip Technology Inc.
7.3.6 SLAVE MODE BUS COLLISION
On a read request from the master, the slave begins shifting data out on the SDAx line. If a bus
collision is detected and the SBCDE bit (I2CxCONH<2> register) is set, then the I2CxBCIF bit
will be set. After detecting the bus collision, the slave goes into Idle mode and waits to be
addressed again. User software can use the I2CxBCIF bit or vectors to the bus collision interrupt
to handle a slave bus collision.
7.3.7 GENERAL CALL OPERATION
The addressing procedure for the I
2
C bus is such that the first byte after a Start condition usually deter-
mines which slave device the master is addressing. The exception is the general call address, which
can address all devices. When this address is used, all the enabled devices respond with an Acknowl-
edge. The general call address is one of the eight addresses reserved for specific purposes by the
I
2
C protocol. It consists of all ‘0’s with R/W = 0. The general call is always a slave write operation.
The general call address is recognized when the General Call Enable bit, GCEN (I2CxCON<7>
or I2CxCONL<7>), is set, as illustrated in Figure 7-9. Following a Start bit detect, 8 bits are shifted
into the I2CxRSR register, and the address is compared against the I2CxADD register and the
general call address.
If the general call address matches, the following events occur:
• An ACK
is generated
• The slave will set the GCSTAT status bit (I2CxSTAT<9>)
• The D/A
and R/W status bits are cleared
• The module generates the SI2CxIF interrupt on the falling edge of the ninth SCLx clock
• The I2CxRSR register is transferred to the I2CxRCV register and the RBF status bit
(I2CxSTAT<1>) is set (during the eighth bit)
• The module waits for the master to send data
When the interrupt is serviced, the cause for the interrupt can be checked by reading the contents of
the GCSTAT status bit to determine if the device address was device-specific or a general call address.
Figure 7-9: General Call Address Detection Timing Diagram (GCEN = 1; AHEN = 0)
Note: The SBCDE and I2CxBCIF bits may not be available on all the devices. Refer to the
specific device data sheet for availability.
Note 1: General call addresses are 7-bit addresses. If configuring the slave for 10-bit
addresses and the A10M and GCEN bits are set, the slave will continue to detect
the 7-bit general call address.
2: The slave will Acknowledge the general call address (7-bit address, 0x00) only if
GCEN is set, and independent of the STRICT and A10M bits.
SCLx (Master)
SDAx (Master)
SDAx (Slave)
SI2CxIF Interrupt
4 51 3
Detecting Start bit enables
1
I
2
C™ Bus State (D) (D) (A)(D)
000 0 0 0 0
D/A
I2CxRCV
RBF
R/W
address detection. If SCIE is set,
All ‘0’s and R/W
= 0 indicates
3
a general call.
Valid address clears D/A
status bit
4
and sets GCSTAT status bit.
R/W
status bit cleared. Slave
5
generates an interrupt.
6
Bus waiting. Slave ready to
6
receive data.
GCSTAT
Slave generates ACK
. Address
loaded into I2CxRCV register.
R/W = 0
(Q)
2
then interrupt will be asserted.
(1)
Note 1: The SCIE bit may not be available in all the devices. Refer to the specific device data sheet for availability.
2 User software clears the interrupt
flag.
(1)
(S)

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