# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 88 © 2005-2011 Microchip Technology Inc.
4.15 DSP ACCUMULATOR INSTRUCTIONS (dsPIC30F, dsPIC33F AND
dsPIC33E DEVICES)
The DSP Accumulator instructions do not have prefetch or accumulator WB ability, but they do
provide the ability to add, negate, shift, load and store the contents of either 40-bit Accumulator.
In addition, the ADD and SUB instructions allow the two accumulators to be added or subtracted
from each other. DSP Accumulator instructions are shown in
Table 4-12 and instruction details
are provided in Section 5. “Instruction Descriptions”.
Table 4-12: DSP Accumulator Instructions
4.16 SCALING DATA WITH THE FBCL INSTRUCTION (dsPIC30F, dsPIC33F AND
dsPIC33E DEVICES)
To minimize quantization errors that are associated with data processing using DSP instructions,
it is important to utilize the complete numerical result of the operations. This may require scaling
data up to avoid underflow (i.e., when processing data from a 12-bit ADC), or scaling data down
to avoid overflow (i.e., when sending data to a 10-bit DAC). The scaling, which must be
performed to minimize quantization error, depends on the dynamic range of the input data which
is operated on, and the required dynamic range of the output data. At times, these conditions
may be known beforehand and fixed scaling may be employed. In other cases, scaling conditions
may not be fixed or known, and then dynamic scaling must be used to process data.
The FBCL instruction (Find First Bit Change Left) can efficiently be used to perform dynamic
scaling, because it determines the exponent of a value. A fixed point or integer value’s exponent
represents the amount which the value may be shifted before overflowing. This information is
valuable, because it may be used to bring the data value to “full scale”, meaning that its numeric
representation utilizes all the bits of the register it is stored in.
The FBCL instruction determines the exponent of a word by detecting the first bit change starting
from the value’s sign bit and working towards the LSB. Since the dsPIC DSC device’s barrel
shifter uses negative values to specify a left shift, the FBCL instruction returns the negated
exponent of a value. If the value is being scaled up, this allows the ensuing shift to be performed
immediately with the value returned by FBCL. Additionally, since the FBCL instruction only
operates on signed quantities, FBCL produces results in the range of -15:0. When the FBCL
instruction returns ‘0’, it indicates that the value is already at full scale. When the instruction
returns -15, it indicates that the value cannot be scaled (as is the case with 0x0 and 0xFFFF).
Table 4-13 shows word data with various dynamic ranges, their exponents, and the value after
scaling each data to maximize the dynamic range. Example 4-23 shows how the FBCL
instruction may be used for block processing.
Instruction Description Accumulator WB?
ADD Add accumulators No
ADD 16-bit signed accumulator add No
LAC Load accumulator No
NEG Negate accumulator No
SAC Store accumulator No
SAC.R Store rounded accumulator No
SFTAC Arithmetic shift accumulator by Literal No
SFTAC Arithmetic shift accumulator by (Wn) No
SUB Subtract accumulators No

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