# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 90 © 2005-2011 Microchip Technology Inc.
4.17 NORMALIZING THE ACCUMULATOR WITH THE FBCL INSTRUCTION
(dsPIC30F, dsPIC33F AND dsPIC33E DEVICES)
The process of scaling a quantized value for its maximum dynamic range is known as
normalization (the data in the third column in
Table 4-13 contains normalized data). Accumulator
normalization is a technique used to ensure that the accumulator is properly aligned before
storing data from the accumulator, and the FBCL instruction facilitates this function.
The two 40-bit accumulators each have 8 guard bits from the ACCxU register, which expands the
dynamic range of the accumulators from 1.31 to 9.31, when operating in Super Saturation mode
(see Section 4.11.1 “Integer and Fractional Data”). However, even in Super Saturation mode,
the Store Rounded Accumulator (SAC.R) instruction only stores 16-bit data (in 1.15 format) from
ACCxH, as described in Section 4.12 “Accumulator Usage (dsPIC30F, dsPIC33F and
dsPIC33E Devices)”. Under certain conditions, this may pose a problem.
Proper data alignment for storing the contents of the accumulator may be achieved by scaling
the accumulator down if ACCxU is in use, or scaling the accumulator up if all of the ACCxH bits
are not being used. To perform such scaling, the FBCL instruction must operate on the ACCxU
byte and it must operate on the ACCxH word. If a shift is required, the ALU’s 40-bit shifter is
employed, using the SFTAC instruction to perform the scaling.
Example 4-24 contains a code
snippet for accumulator normalization.
Example 4-24: Normalizing with FBCL
; assume an operation in ACCA has just completed (SR intact)
; assume the processor is in super saturation mode
; assume ACCAH is defined to be the address of ACCAH (0x24)
MOV #ACCAH, W5 ; W5 points to ACCAH
BRA OA, FBCL_GUARD ; if overflow we right shift
FBCL_HI:
FBCL [W5], W0 ; extract exponent for left shift
BRA SHIFT_ACC ; branch to the shift
FBCL_GUARD:
FBCL [++W5], W0 ; extract exponent for right shift
ADD.B W0, #15, W0 ; adjust the sign for right shift
SHIFT_ACC:
SFTAC A, W0 ; shift ACCA to normalize

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