# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 -- Serial Peripheral Interface

- 1
- 2
…
- 29
- 30
- 31
- 32
- 33
…
- 41
- 42

 2014 Microchip Technology Inc. DS70005185A-page 31
Serial Peripheral Interface (SPI) Module
3.5.5 SPI SLAVE/FRAMED SLAVE MODE
In SPI Slave/Framed Slave mode, the module gets both its clock and frame synchronization
signal from the master module (see Figure 3-14). This mode is enabled by setting the MSTEN
bit (SPIxCON1<5>) to ‘0’, the FRMEN bit (SPIxCON2<15>) to ‘1’ and the SPIFSD bit
(SPIxCON2<14>) to ‘1’.
In this mode, both the SCKx and SSx
pins are inputs. The SSx pin is sampled on the sample
edge of the SPIx clock. When SSx
is sampled at its active state, data is transmitted on the
appropriate transmit edge of SCKx.
Figure 3-14: SPIx Slave/Framed Slave Connection Diagram
3.6 SPIx Receive Only Operation
Setting the Disable SDOx Pin (DISSDO) control bit (SPIxCON1<11>) disables transmission at the
SDOx pin. This allows the SPIx module to be configured for a Receive Only mode of operation. The
SDOx pin is controlled by the respective port function if the DISSDO bit is set. The DISSDO function
is applicable to all SPI operating modes.
3.7 SPIx Error Handling
If a new data word has been shifted into the SPIxSR register and the previous SPIxBUF register
contents have not been read, the SPIROV bit (SPIxSTAT<6>) is set. Any received data in the
SPIxSR register is not transferred and further data reception is disabled until the SPIROV bit is
cleared. The SPIROV bit is not cleared automatically by the module; it must be cleared by the
user application.
The SPIxIF bit is set when the SPIRBF bit (SPIxSTAT<0>) is set. The interrupt flag cannot be
cleared by the hardware; it must be reset in software. The actual SPIx interrupt is generated only
when the corresponding SPIxIE bit is set in the IECx Control register.
In addition, the SPIx Error Interrupt Flag (SPIxEIF or SPFxIF for PIC24F devices) is set when the
SPIROV bit is set. This interrupt flag must be cleared in software. The actual SPIx error interrupt
is generated only when the corresponding SPIxEIE bit is set in the IECx Control register.
SDOx
SDIx
dsPIC33/PIC24
Serial Clock
SSx
SCKx
Frame Sync
Pulse
SDIx
SDOx
PROCESSOR 2
SSx
SCKx
(SPIx Slave/Framed Slave)

- 1
- 2
…
- 29
- 30
- 31
- 32
- 33
…
- 41
- 42