# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 -- Serial Peripheral Interface

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dsPIC33/PIC24 Family Reference Manual
DS70005185A-page 10  2014 Microchip Technology Inc.
Register 2-3: SPIxCON2: SPIx Control Register 2
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0
FRMEN SPIFSD FRMPOL/
SPIFPOL
(2)
— — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — FRMDLY/
SPIFE
(2)
SPIBEN
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 FRMEN: Framed SPIx Support bit
1 = Framed SPIx support is enabled (the SSx
pin is used as a frame sync pulse input/output)
0 = Framed SPIx support is disabled
bit 14 SPIFSD: SPIx Frame Sync Pulse Direction Control bit
1 = Frame sync pulse input (slave)
0 = Frame sync pulse output (master)
bit 13 FRMPOL/SPIFPOL: SPIx Frame Sync Pulse Polarity bit
(2)
1 = Frame sync pulse is active-high
0 = Frame sync pulse is active-low
bit 12-2 Unimplemented: Read as ‘0’
bit 1 FRMDLY/SPIFE: SPIx Frame Sync Pulse Edge Select bit
(2)
1 = Frame sync pulse coincides with the first bit clock
0 = Frame sync pulse precedes the first bit clock
bit 0 SPIBEN: SPIx Enhanced Buffer Enable bit
(1)
1 = Enhanced buffer is enabled
0 = Enhanced buffer is disabled (Legacy mode)
Note 1: These bits are unimplemented on the dsPIC33F/PIC24H devices as they do not support the
Enhanced Buffer mode.
2: The SPIFPOL and SPIFE bit names are used for PIC24F devices.

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