# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 -- Errata

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PIC24FJ64GA004 FAMILY
DS80000470H-page 14  2009-2013 Microchip Technology Inc.
34. Module: RTCC
Under certain circumstances, the value of the Alarm
Repeat Counter (ALCFGRPT<7:0>) may be unex-
pectedly decremented. This happens only when a
byte write to the upper byte of ALCFGRPT is per-
formed in the interval between a device POR/BOR
and the first edge from the RTCC clock source.
Work around
Do not perform byte writes on ALCFGRPT,
particularly the upper byte.
Alternatively, wait until one period of the SOSC
has completed before performing byte writes to
ALCFGRPT.
Affected Silicon Revisions
35. Module: SPI (Master Mode)
In Master mode, the SPIx Interrupt Flag (SPIxIF)
and the SPIRBF bit (SPIxSTAT<0>) may both
become set one-half clock cycle early, instead of
on the clock edge. This occurs only under the
following circumstances:
• Enhanced Buffer mode is disabled
(SPIBEN = 0); and
• the module is configured for serial data output
changes on transition from clock active to clock
Idle state (CKE = 1).
If the application is using the interrupt flag to
determine when data to be transmitted is written to
the transmit buffer, the data currently in the buffer
may be overwritten.
Work around
Before writing to the SPIx buffer, check the SCKx pin
to determine if the last clock edge has passed.
Example 1 (below) demonstrates a method for doing
this. In this example, the RD1 pin functions as the
SPIx clock, SCKx, which is configured as Idle low.
Affected Silicon Revisions
36. Module: I
2
C (Master Mode)
Under certain circumstances, a module operating
in Master mode may Acknowledge its own com-
mand addressed to a slave device. This happens
when the following occurs:
• 10-Bit Addressing mode is used (A10M = 1);
and
• the I
2
C master has the same two upper
address bits (I2CADD<9:8>) as the addressed
slave module.
In these cases, the master also Acknowledges the
address command and generates an erroneous
I
2
C
slave interrupt, as well as the
I
2
C
master interrupt.
Work around
Several options are available:
• When using 10-Bit Addressing mode, make
certain that the master and slave devices do not
share the same 2 MSbs of their addresses.
If this cannot be avoided:
• Clear the A10M bit (I2CxCON<10> = 0) prior to
performing a Master mode transmit.
• Read the ADD10 bit (I2CxSTAT<8>) to check
for a full 10-bit match whenever a slave I
2
C
interrupt occurs on the master module.
Affected Silicon Revisions
EXAMPLE 1: CHECKING THE STATE OF SPIxIF AGAINST THE SPIx CLOCK
A3/
A4
B4 B5
B8
X X X
A3/
A4
B4 B5
B8
X
A3/
A4
B4 B5
B8
X X X
X
while(IFS0bits.SPI1IF == 0){} //wait for the transmission to complete
while(PORTDbits.RD1 == 1){} //wait for the last clock to finish
SPI1BUF = 0xFF; //write new data to the buffer

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