# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 -- Serial Peripheral Interface

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dsPIC33/PIC24 Family Reference Manual
DS70005185A-page 22  2014 Microchip Technology Inc.
3.4 Enhanced Buffer Master and Slave Modes
The dsPIC33F/PIC24H devices do not support the Enhanced Buffer mode. The operation of
Enhanced Buffer Master and Slave modes is very similar to Standard Master and Slave modes.
The difference is that data can be thought of as moving from the Shift register to a receive FIFO
buffer and moving from the transmit FIFO buffer to the Shift register. The relationships in
Enhanced Buffer mode are shown in Figure 3-6.
Figure 3-6: SPIx Master/Slave Connection (Enhanced Buffer Modes)
Shift Register
(SPIxSR)
SDIx
SDOx
PROCESSOR 2
SCKx
SSx
(1)
Shift Register
(SPIxSR)
MSb LSb
SDOx
SDIx
PROCESSOR 1
Serial Clock
SSEN (SPIxCON1<7>) = 1,
Note 1: The use of the SSx
pin in Slave mode is optional.
2: The user application must write transmit data to read the received data from the SPIxBUF register.
The SPIxTXB and SPIxRXB registers are memory-mapped to the SPIxBUF register.
SSx
(1)
SCKx
MSTEN (SPIxCON1<5> = 1 and
SPIx Buffer
(SPIxBUF)
(2)
SPIBEN (SPIxCON2<0>) = 1
MSTEN (SPIxCON1<5>) = 0 and
SPIBEN (SPIxCON2<0> = 1
TransferTransfer
MSb LSb
Transfer
Transfer
(SPIx Enhanced Buffer Master) (SPIx Enhanced Buffer Slave)
8-Level FIFO
Receive Buffer
8-Level FIFO
Transmit Buffer
8-Level FIFO
Receive Buffer
8-Level FIFO
Transmit Buffer
SPIx Buffer
(SPIxBUF)
(2)

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