# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Family Data Sheet

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© 2011-2012 Microchip Technology Inc. Preliminary DS39997C-page 147
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
REGISTER 12-4: T5CON CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
TON
(2)
— TSIDL
(1)
— — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0
— TGATE
(2)
TCKPS<1:0>
(2)
— — TCS
(2)
—
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 TON: Timer5 On bit
(2)
1 = Starts 16-bit Timer3
0 = Stops 16-bit Timer3
bit 14 Unimplemented: Read as ‘0’
bit 13 TSIDL: Stop in Idle Mode bit
(1)
1 = Discontinue timer operation when device enters Idle mode
0 = Continue timer operation in Idle mode
bit 12-7 Unimplemented: Read as ‘0’
bit 6 TGATE: Timer5 Gated Time Accumulation Enable bit
(2)
When TCS = 1:
This bit is ignored.
When TCS =
0:
1 = Gated time accumulation enabled
0 = Gated time accumulation disabled
bit 5-4 TCKPS<1:0>: Timer5 Input Clock Prescale Select bits
(2)
11 = 1:256 prescale value
10 = 1:64 prescale value
01 = 1:8 prescale value
00 = 1:1 prescale value
bit 3-2 Unimplemented: Read as ‘0’
bit 1 TCS: Timer5 Clock Source Select bit
(2)
1 = External clock from T5CK pin
0 = Internal clock (F
OSC/2)
bit 0 Unimplemented: Read as ‘0’
Note 1: When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (T4CON<3>), the TSIDL bit
must be cleared to operate the 32-bit timer in Idle mode.
2: When the 32-bit timer operation is enabled (T32 = 1) in the Timer Control (T4CON<3>) register, these bits
have no effect.
Note: This register is available in PIC24FJ32MC101/102/104 devices only.

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