# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 224 © 2005-2011 Microchip Technology Inc.
DIV.S
Signed Integer Divide
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} DIV.S{W} Wm, Wn
DIV.SD Wm, Wn
Operands: Wm ∈ [ W0 ... W15] for word operation
Wm ∈ [ W0, W2, W4 ... W14] for double operation
Wn ∈ [ W2 ... W15]
Operation: For word operation (default):
Wm → W0
If (Wm<15> = 1):
0xFFFF → W1
Else:
0x0 → W1
W1:W0 / Wn → W0
Remainder → W1
For double operation (DIV.SD):
Wm + 1:Wm → W1:W0
W1:W0 / Wn → W0
Remainder → W1
Status Affected: N, OV, Z, C
Encoding: 1101 1000 0ttt tvvv vW00 ssss
Description: Iterative, signed integer divide, where the dividend is stored in Wm (for a
16-bit by 16-bit divide) or Wm + 1:Wm (for a 32-bit by 16-bit divide) and
the divisor is stored in Wn. In the default word operation, Wm is first
copied to W0 and sign-extended through W1 to perform the operation. In
the double operation, Wm + 1:Wm is first copied to W1:W0. The 16-bit
quotient of the divide operation is stored in W0, and the 16-bit remainder
is stored in W1.
This instruction must be executed 18 times using the REPEAT instruction
(with an iteration count of 17) to generate the correct quotient and
remainder. The N flag will be set if the remainder is negative and cleared
otherwise. The OV flag will be set if the divide operation resulted in an
overflow and cleared otherwise. The Z flag will be set if the remainder is
‘0’ and cleared otherwise. The C flag is used to implement the divide
algorithm and its final value should not be used.
The ‘t’ bits select the most significant word of the dividend for the double
operation. These bits are clear for the word operation.
The ‘v’ bits select the least significant word of the dividend.
The ‘W’ bit selects the dividend size (‘0’ for 16-bit, ‘1’ for 32-bit).
The ‘s’ bits select the divisor register.

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