# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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© 2005-2011 Microchip Technology Inc. DS70157F-page 153
Section 5. Instruction Descriptions
Instruction
Descriptions
5
BSET
Bit Set in Ws
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} BSET{.B} Ws, #bit4
[Ws],
[Ws++],
[Ws--],
[++Ws],
[--Ws],
Operands: Ws ∈ [W0 ... W15]
bit4 ∈ [0 ... 7] for byte operation
bit4 ∈ [0 ... 15] for word operation
Operation: 1 → Ws<bit4>
Status Affected: None
Encoding: 1010 0000 bbbb 0B00 0ppp ssss
Description: Set the bit in register Ws specified by ‘bit4’. Bit numbering begins with the
Least Significant bit (bit 0) and advances to the Most Significant bit (bit 7
for byte operations, bit 15 for word operations). Register direct or indirect
addressing may be used for Ws.
The ‘b’ bits select value bit4 of the bit position to be cleared.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source/destination register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: When this instruction operates in Word mode, the source
register address must be word-aligned.
3: When this instruction operates in Byte mode, ‘bit4’ must be
between 0 and 7.
4: In dsPIC33E and PIC24E devices, this instruction uses the
DSRPAG register for indirect address generation in Extended
Data Space.
Words: 1
Cycles:
1
(1)
Note 1:
In dsPIC33E and PIC24E devices, the listed cycle count does not apply to read and
read-modify-write operations on non-CPU Special Function Registers. For more
details, see
Note 3
in
Section 3.2.1 “Multi-Cycle Instructions”
.

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