# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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dsPIC33/PIC24 Family Reference Manual
DS70000195F-page 28  2007-2014 Microchip Technology Inc.
5.6 Generating a Repeated Start Bus Event
Setting the RSEN bit (I2CxCON<1> or I2CxCONL<1>) enables the generation of a master
Repeated Start sequence, as illustrated in Figure 5-8.
To generate a Repeated Start condition, the user software sets the RSEN bit (I2CxCON<1> or
I2CxCONL<1>). The master module asserts the SCLx pin low. When the module samples the
SCLx pin low, the module releases the SDAx pin for 1 T
BRG. When the BRG times out and the
module samples SDAx high, the module deasserts the SCLx pin. When the module samples the
SCLx pin high, the BRG reloads and begins counting. SDAx and SCLx must be sampled high for
1 T
BRG. This action is then followed by assertion of the SDAx pin low for 1 TBRG while SCLx is
high.
The following is the Repeated Start sequence:
1. The slave detects the Start condition, sets the S status bit (I2CxSTAT<3>) and clears the
P status bit (I2CxSTAT<4>).
2. The RSEN bit is automatically cleared.
3. The I
2
C module generates the MI2CxIF interrupt.
5.6.1 IWCOL STATUS FLAG
If the user software writes the I2CxTRN register when a Repeated Start sequence is in progress,
the IWCOL status bit (I2CxSTAT<7>) is set and the contents of the buffer are not changed (the
write does not occur).
Figure 5-8: Master Repeated Start Timing Diagram
Note: The lower 5 bits of the I2CxCON or I2CxCONL register must be ‘0’ (master logic
inactive) before attempting to set the RSEN bit.
Note: Because queuing of events is not allowed, writing of the lower 5 bits of the I2CxCON
or I2CxCONL register is disabled until the Repeated Start condition is complete.
SCLx (Master)
SDAx (Master)
S
RSEN
MI2CxIF Interrupt
TBRG
1 2 3 5
Writing RSEN = 1 initiates a master Repeated Start event.
1
TBRG
BRG starts. Module drives SCLx low and
The BRG times out. Module releases SCLx.
2
BRG restarts.
The BRG times out. Module drives SDAx low.
3
Slave logic detects Start. Module sets S = 1 and P = 0.
4
I
2
C™ Bus State
(Q)
P
TBRG
(Q)
4
BRG restarts.
The BRG times out. Module drives SCLx low.
5
Module clears RSEN. Master generates the interrupt.
(Q)
releases SDAx.
(S)

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