# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Reset

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PIC24F Family Reference Manual
DS39712D-page 7-18 © 2011 Microchip Technology Inc.
The Reset time line in Figure 7-7 displays an example of when the EC clock source is used as
the system clock. This example is similar to the one provided in Figure 7-6, except that the
Oscillator Start-up Timer delay, T OST, does not occur.
Figure 7-7: Device Reset Delay, EC and ECPLL Clocks
POR Circuit Threshold Voltage
Internal Power-on Reset Pulse
TPOR
(2)
VDD
Oscillator Released to System
POR
System Reset Released
Note 1: Delay times shown are not drawn to scale.
2: T
POR = Power-on Reset delay.
3: T
STARTUP = TVREG if the on-chip regulator is enabled or TPWRT if it is disabled.
4: T
RST = Internal State Reset time.
5: ECPLL mode shown. When PLL is disabled, T
LOCK is not inserted. The system clock is released immediately
following T
RST.
OSC Delay
(1)
T STARTUP
(3)
T RST
(4)
SYSRST
(1)
TLOCK
(5)

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