# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Serial Peripheral Interface

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© 2007 Microchip Technology Inc. Advance Information DS39699B-page 23-6
Section 23. Serial Peripheral Interface (SPI)
Serial Peripheral
Interface (SPI)
23
bit 1 SPIxTBF: SPIx Transmit Buffer Full Status bit
1 = Transmit not yet started, SPIxTXB is full
0 = Transmit started, SPIxTXB is empty
Standard Buffer Mode
Automatically set in hardware when core writes SPIxBUF location, loading SPIxTXB.
Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR.
Enhanced Buffer Mode
Automatically set in hardware when CPU writes SPIxBUF location, loading the last available buffer location.
Automatically cleared in hardware when a buffer location is available for a CPU write.
bit 0 SPIxRBF: SPIx Receive Buffer Full Status bit
1 = Receive complete, SPIxRXB is full
0 = Receive is not complete, SPIxRXB is empty
Standard Buffer Mode
Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB.
Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB.
Enhanced Buffer Mod
e
Automatically set in hardware when SPIx transfers data from SPIxSR to buffer, filling the last unread
buffer location.
Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR.
Register 23-1: SPIxSTAT: SPIx Status Register (Continued)

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