# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Comparator with Blanking

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© 2010 Microchip Technology Inc. Preliminary DS39741A-page 48-19
Section 48. Comparator with Blanking
Comparator with
Blanking
48
48.5 COMPARATOR INTERRUPTS
The Comparator Interrupt Flag (CMIF) bit (IFS1<2>) is set when the synchronized output value
of any of the comparator changes with respect to the last read value. The following bits can be
read by the user application to detect an event:
• C1EVT – Comparator 1 Event bit (CMSTAT<8>)
• C2EVT – Comparator 2 Event bit (CMSTAT<9>)
• C3EVT – Comparator 3 Event bit (CMSTAT<10>)
User-assigned software can read the CxEVT and CxOUT bits to determine the change that
occurred. Because it is possible to write a ‘1’ to this register, a simulated interrupt can be software
initiated. Both the CMIF and CxEVT bits must be reset by clearing them in software. These bits
can be cleared in the Interrupt Service Routine (ISR). For more information, refer to the
Section 8. “Interrupts” (DS39707) in the “PIC24F Family Reference Manual”.
48.5.1 Interrupt Operation During Sleep Mode
If a comparator is enabled and the PIC24F device is placed in Sleep mode, the comparator
remains active. If the Comparator interrupt is enabled in the Interrupt module, it remains
functional. Under these conditions, a comparator interrupt event will wake-up the device from
Sleep mode.
Each operational comparator consumes additional current. To minimize power consumption in
Sleep mode, turn off the comparators before entering Sleep mode by disabling the CON
bit (CMxCON<15>). If the device wakes up from Sleep mode, the contents of the CMxCON
register are not affected. For more information on Sleep mode, refer to
Section 10. “Power-Saving Features” (DS39698) in the “PIC24F Family Reference Manual”.
48.5.2 Interrupt Operation During Idle Mode
The comparator remains active in Idle mode. Comparator interrupt operation during Idle mode is
controlled by the Comparator Idle Mode (CMIDL) bit (CMSTAT<15>). If CMIDL = 0, normal
interrupt operation continues. If CMIDL = 1, the comparator continues to operate, but it does not
generate interrupts.
For more information on Idle mode, refer to Section 10. “Power-Saving Features” (DS39698)
in the “PIC24F Family Reference Manual”.
48.5.3 Effects of a Reset State
A device Reset forces the CMxCON register to its Reset state, causing the comparator modules
to be turned off (CON = 0). However, the input pins multiplexed with analog input sources are
configured as analog inputs by default on device Reset. The I/O configuration for these pins is
determined by the setting of the ADxPCFGL or ADxPCFGH register. Therefore, device current
is minimized when analog inputs are present at Reset time.
48.5.4 Analog Input Connection Considerations
A simplified circuit for an analog input is illustrated in Figure 48-6. A maximum source impedance
of 10 kΩ is recommended for the analog sources. Any external component connected to an
analog input pin, such as a capacitor or a Zener diode, should have little leakage current.
Note: The comparison required for generating interrupts is based on the current comparator
state and the last read value of the comparator outputs. Reading the C1OUT, C2OUT
and C3OUT bits in the CMxCON register will update the values used for the interrupt
generation.

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