# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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 2007-2014 Microchip Technology Inc. DS70000195F-page 39
Inter-Integrated Circuit™ (I
2
C™)
7.3.3 7-BIT ADDRESS AND SLAVE WRITE WITH THE AHEN AND DHEN BITS
The slave device reception, with the AHEN and DHEN bits set, operates with extra interrupts and
clock stretching added after the eighth falling edge of SCLx. These additional interrupts allow the
slave software to decide whether it wants to ACK
the receive address or data byte, rather than
the hardware. This functionality adds support for the PMBus™ that was not present on previous
versions of this module.
Note: The SI2CxIF interrupt is still set after the ninth falling edge of the SCLx clock, even
if there is no clock stretching and the RBF bit has been cleared. The SI2CxIF
interrupt is not asserted if a NACK is sent to the master.

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