# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Motor Control PWM

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© 2010 Microchip Technology Inc. Preliminary DS39735A-page 47-37
Section 47. Motor Control PWM
Motor Control
PWM
47
47.13 PWM FAULT HANDLING
There are two Fault pins, FLTxA and FLTxB, associated with the PWM module. When
asserted, these pins can optionally drive each of the PWM I/O pins to a defined state. This
action takes place without software intervention, so Fault events can be managed quickly.
These Fault pins can have other multiplexed functions depending on the PIC24F device
variant. When used as a Fault input, each Fault pin is readable using its corresponding PORT
register. The FLTxA
and FLTxB pins function as active low inputs so that it is easy to inclusively
OR many sources to the same input through an external pull-up resistor. When not used with
the PWM module, these pins can be used as general purpose I/O or for another multiplexed
function. Each Fault pin has its own Interrupt vector, interrupt flag bit, interrupt enable bit and
interrupt priority bits.
The function of the FLTxA
pin is controlled by the Fault A Configuration (PxFLTACON) register
and the function of the FLTxB
pin is controlled by the Fault B Configuration (PxFLTBCON)
register.
47.13.1 Fault Pin Enable Bits
The PxFLTACON and PxFLTBCON registers each have four Fault Input Enable (FAEN<4:1>
and FBEN<4:1>) bits that determine whether a particular pair of PWM I/O pins is to be
controlled by the Fault input pin. To enable a specific PWM I/O pin pair for Fault overrides, the
corresponding bit should be set in the PxFLTACON or PxFLTBCON register.
If all enable bits are cleared in the PxFLTACON or PxFLTBCON registers, that Fault input pin
has no effect on the PWM module and no Fault interrupts are produced.
47.13.2 Fault States
The PxFLTACON and PxFLTBCON Special Function Registers each have eight bits that
determine the state of each PWM I/O pin when the Fault input pin becomes active. When
these bits are cleared, the PWM I/O pin is driven to the inactive state. If the bit is set, the PWM
I/O pin is driven to the active state. The active and inactive states are referenced to the polarity
defined for each PWM I/O pin (set by HPOL and LPOL Configuration bits).
A special case exists when a PWM module I/O pair is in Complementary PWM Output mode
and both pins are programmed to be active on a Fault condition. The high-side pin will always
have priority in Complementary PWM Output mode, so that both I/O pins cannot be driven
active simultaneously.
47.13.3 Fault Input Modes
Each of the Fault input pins has two modes of operation:
 Latched Mode: When the Fault pin is driven low, the PWM outputs go to the states defined in
the PxFLTACON and PxFLTBCON registers. The PWM outputs remain in this state until the
Fault pin is driven high and the corresponding interrupt flag (FLTxAIF or FLTxBIF) has been
cleared in software. When both of these actions have occurred, the PWM outputs return to
normal operation at the beginning of the next PWM period or half-period boundary, regard-
less of the Immediate Update Enable (IUE) bit value. If the interrupt flag is cleared before the
Fault condition ends, the PWM module waits until the Fault pin is no longer asserted to
restore the outputs.
 Cycle-by-Cycle Mode: When the Fault input pin is driven low, the PWM outputs remain in
the defined Fault states for as long as the Fault pin is held low. After the Fault pin is driven
high, the PWM outputs return to normal operation at the beginning of the following PWM
period (or half-period boundary in center-aligned modes) even when immediate updates
are enabled.
The operating mode for each Fault input pin is selected using the Fault A Mode (FLTAM) bit
and Fault B Mode (FLTBM) bit (PxFLTACON<7> and PxFLTBCON<7>).

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