# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Oscillator

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PIC24F Family Reference Manual
DS39700C-page 6-20 © 2009 Microchip Technology Inc.
6.6.2.1 SYSTEM CLOCK GENERATION
The system clock is generated from the 96 MHz branch using a configurable postscaler/divider
to generate a range of frequencies for the system clock multiplexer. The output of the multiplexer
is further passed through a fixed divide-by-3 divider and the final output is used as the system
clock. Figure 6-8 shows this logic in the system clock subblock. Since the source is a 96 MHz
signal, the possible system clock frequencies are listed in Table 6-3. The available system clock
options are always the same, regardless of the setting of the PLLDIV Configuration bits.
Table 6-3: System Clock Options for 96 MHz PLL Block
6.6.2.2 USB CLOCK GENERATION
For PIC24F devices with USB functionality, the Primary Oscillator combined with this PLL block
can be used as a valid clock source for USB operation. In some PIC24F devices, the FRC
Oscillator that meets USB clocking accuracy requirements can be combined with this PLL block
providing another option for a valid clock source for USB operation. There is no provision to pro-
vide a separate external 48 MHz clock to the USB module. The USB module sources its clock
signal from the 96 MHz PLL. Due to the requirement that a 4 MHz input must be provided to gen-
erate the 96 MHz signal, the oscillator operation is limited to a range of possible values. Table 6-4
shows the valid oscillator configurations (i.e., ECPLL, HSPLL, XTPLL and FRCPLL) for USB
operation. This sets the correct PLLDIV configuration for a specified oscillator frequency and the
output frequency of the USB clock branch is always 48 MHz.
Table 6-4: Valid Oscillator Configurations for USB Operations
MCU Clock Division
(CPDIV<1:0>)
System Clock Frequency
(Instruction Rate in MIPS)
None (00) 32 MHz (16)
÷2 (01) 16 MHz (8)
÷4 (10) 8 MHz (4)
(1)
÷8 (11) 4 MHz (2)
(1)
Note 1: These options are not compatible with USB operation. They may be used whenever
the PLL branch is selected and the USB module is disabled.
Input Oscillator
Frequency
Clock Mode
PLL Division
(PLLDIV<2:0>)
48 MHz ECPLL ÷12 (111)
32 MHz ECPLL ÷ 8 (110)
24 MHz HSPLL, ECPLL ÷6 (101)
20 MHz HSPLL, ECPLL ÷5 (100)
16 MHz HSPLL, ECPLL ÷4 (011)
12 MHz HSPLL, ECPLL ÷3 (010)
8 MHz ECPLL, XTPLL, FRCPLL
(1)
÷2 (001)
4 MHz ECPLL, XTPLL, FRCPLL
(1)
÷1 (000)
Note 1: FRCPLL with ±0.25% accuracy can be used for USB operation.
Note: For USB devices, the use of a Primary Oscillator or external clock source with a
frequency above 32 MHz does not imply that the device’s system clock can be run
at the same speed when the USB module is not used. The maximum system clock
for all PIC24F devices is 32 MHz.
Because of USB clocking accuracy requirements (±0.25%), not all PIC24F devices
support the use of the FRCPLL system clock configuration for USB operation. Refer
to the specific device data sheet for details on the FRC Oscillator module.

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