# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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© 2005-2011 Microchip Technology Inc. DS70157F-page 379
Section 5. Instruction Descriptions
Instruction
Descriptions
5
RLNC
Rotate Left Ws without Carry
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} RLNC{.B} Ws, Wd
[Ws], [Wd]
[Ws++], [Wd++]
[Ws--], [Wd--]
[++Ws], [++Wd]
[--Ws], [--Wd]
Operands: Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]
Operation: For byte operation:
(Ws<6:0>) → Wd<7:1>
(Ws<7>) → Wd<0>
For word operation:
(Ws<14:0>) → Wd<15:1>
(Ws<15>) → Wd<0>
Status Affected: N, Z
Encoding: 1101 0010 0Bqq qddd dppp ssss
Description: Rotate the contents of the source register Ws one bit to the left and place
the result in the destination register Wd. The Most Significant bit of Ws is
stored in the Least Significant bit of Wd, and the Carry flag is not
affected. Either register direct or indirect addressing may be used for Ws
and Wd.
The ‘B’ bit selects byte or word operation (‘0’ for byte, ‘1’ for word).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
Words: 1
Cycles:
1
(1)
Note 1:
In dsPIC33E and PIC24E devices, the listed cycle count does not apply to read and
read-modify-write operations on non-CPU Special Function Registers. For more
details, see
Note 3
in
Section 3.2.1 “Multi-Cycle Instructions”
.

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