# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Data Memory

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© 2007 Microchip Technology Inc. Advance Information DS39717A-page 3-5
Section 3. Data Memory
Data Memory
3
3.3 DATA ALIGNMENT
To maintain backward compatibility with PIC
®
devices and to improve the data space memory
usage efficiency, the PIC24F instruction set supports both word and byte operations. As a con-
sequence of byte accessibility, all effective address calculations are internally scaled to step
through word-aligned memory.
The LSb of a 16-bit data address is ignored during word operations. Word data is aligned in the
little-endian format with the Least Significant Byte (LSB) at the even address (LSb = 0) and the
Most Significant Byte (MSB) at the odd address (LSb = 1).
For byte operations, the LSb of the data address is used to select the byte that is accessed.
Figure 3-2 shows the data alignment for word and byte operations.
Figure 3-2: Data Alignment
Data byte reads will read the complete word, which contains the byte, using the LSb of any EA
to determine which byte to select. The selected byte is placed onto the LSB of the data path. That
is, data memory and registers are organized as two parallel, byte-wide entities with shared (word)
address decode but separate write lines. Data byte writes only write to the corresponding side of
the array or register which matches the byte address.
All effective address calculations are automatically adjusted depending on whether a byte or a
word access is performed. For example, an address will be incremented by 2 for a word
operation that post-increments the Address Pointer. Similarly, the address will be incremented
by 1 for a byte operation that post-increments the Address Pointer.
All word accesses must be aligned to an even address. Misaligned word data fetches are not
supported, so care must be taken when mixing byte and word operations, or translating from 8-bit
MCU code. If a misaligned read or write is attempted, an address error trap will be generated. If
the error occurred on a read, the instruction underway is completed; if it occurred on a write, the
instruction will be executed but the write will not occur. In either case, a trap is then executed,
allowing the system and/or user to examine the machine state prior to execution of the address
Fault. For additional details regarding the interrupts, refer to Section 8. “Interrupts”.
All byte loads into any W register are loaded into the Least Significant Byte. The Most Significant
Byte is not modified.
A sign-extend instruction (SE) is provided to allow users to translate 8-bit signed data to 16-bit
signed values. Alternatively, for 8-bit unsigned data, users can clear the MSB of any W register
by executing a zero-extend (ZE) instruction on the appropriate address.
Although most instructions are capable of operating on word or byte data sizes, it should be noted
that some instructions operate only on words.
15 8 7 0
0001
0003
0005
0000
0002
0004
Byte 1
Byte 3
Byte 5
LSB
MSB
Word 0
Word 1
0006
0008
Long Word<15:0> 000A
Long Word<31:16> 000C
Byte 0
Byte 2
Byte 4

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