# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Motor Control PWM

- 1
- 2
…
- 44
- 45
- 46
- 47
- 48
- 49
- 50

DS39735A-page 47-46 Preliminary © 2010 Microchip Technology Inc.
47.16 REGISTER MAP
A summary of the registers associated with the PIC24F Family Motor Control PWM module is provided in T
Table 47-7: Registers Associated with 8-Output MCPWM Module
Name
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
PxTCON PTEN
 PTSIDL      PTOPS<3:0> PTCKPS<1:0> PTMOD<1:0
PxTMR PTDIR PWM Time Base Register
PxTPER
 PWM Time Base Period Register
PxSECMP SEVTDIR PWM Special Event Compare Register
PWMxCON1
     PMOD3 PMOD2 PMOD1  PEN3H PEN2H PEN1H  PEN3L PEN2L PEN1
PWMxCON2     SEVOPS<3:0>      IUE OSYNC UDIS
PxDTCON1 DTBPS<1:0> Dead Time B Value Register DTAPS<1:0> Dead Time A Value Register
PxDTCON2
          DTS3A DTS3I DTS2A DTS2I DTS1A DT
PxFLTACON
  FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L FLTAM     FAEN3 FAEN2 FAEN1
PxFLTBCON   FBOV3H FBOV3L FBOV2H FBOV2L FBOV1H FBOV1L FLTBM     FBEN3 FBEN2 FBEN
PxOVDCON   POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L   POUT3H POUT3L POUT2H POUT2L POUT1H POUT
PxDC1 PWM Duty Cycle 1 Register
PxDC2 PWM Duty Cycle 2 Register
PxDC3 PWM Duty Cycle 3 Register
PWMKEY
(3)
PWMLOCK<15:0>
Legend:  = unimplemented, read as 0; x = bit is unknown
Note 1: The Reset condition of the PEN3H:PEN1H and PEN3L:PEN1L bits depends on the value of the PWMPIN Configuration bit in the FPOR Device Configuration register. When P
1 and when PWMPIN is set to 1, Reset values are 0.
2: In devices where the PWMLOCK bit is present in the FOSCSEL Configuration register, the Reset value for the FAEN<3:1> and FBEN<3:1> bits is 1 when PWMLOCK is se
Reset value for these bits is 0. Refer to the specific device data sheet for further details.
3: This register is implemented only in devices where the PWMLOCK bit is present in the FOSCSEL Configuration register. Refer to the specific device data sheet for availabili

- 1
- 2
…
- 44
- 45
- 46
- 47
- 48
- 49
- 50