# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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© 2005-2011 Microchip Technology Inc. DS70157F-page 305
Section 5. Instruction Descriptions
Instruction
Descriptions
5
MUL.SS
Integer 16x16-bit Signed Multiply
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} MUL.SS Wb, Ws, Wnd
[Ws],
[Ws++],
[Ws--],
[++Ws],
[--Ws],
Operands: Wb ∈ [W0 ... W15]
Ws ∈ [W0 ... W15]
Wnd ∈ [W0, W2, W4 ... W12]
Operation: signed (Wb) * signed (Ws) → Wnd:Wnd + 1
Status Affected: None
Encoding:
1011 1001 1www wddd dppp ssss
Description: Multiply the contents of Wb with the contents of Ws, and store the 32-bit
result in two successive working registers. The least significant word of
the result is stored in Wnd (which must be an even numbered working
register), and the most significant word of the result is stored in
Wnd + 1. Both source operands and the result Wnd are interpreted as
two’s complement signed integers. Register direct addressing must be
used for Wb and Wnd. Register direct or register indirect addressing
may be used for Ws.
The ‘w’ bits select the address of the base register.
The ‘d’ bits select the address of the lower destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note 1: This instruction operates in Word mode only.
2: Since the product of the multiplication is 32 bits, Wnd must be
an even working register. See Figure 4-2 for information on
how double words are aligned in memory.
3: Wnd may not be W14, since W15<0> is fixed to zero.
4: The IF bit and the US<1:0> bits in the CORCON register have
no effect on this operation.
Words: 1
Cycles:
1
(1)
Note 1:
In dsPIC33E and PIC24E devices, the listed cycle count does not apply to read and
read-modify-write operations on non-CPU Special Function Registers. For more
details, see
Note 3
in
Section 3.2.1 “Multi-Cycle Instructions”
.

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