# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Oscillator

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© 2009 Microchip Technology Inc. DS39700C-page 6-5
Section 6. Oscillator
Oscillator
6
6.4 CONTROL REGISTERS
The operation of the oscillator is controlled by three (or up to five for some devices) Special
Function Registers (SFRs):
• OSCCON
• CLKDIV
• OSCTUN
• REFOCON (select devices only)
• CLKDIV2 (select devices only)
6.4.1 Oscillator Control Register (OSCCON)
The OSCCON register (Register 6-1) is the main control register for the oscillator. It controls
clock source switching and allows the monitoring of clock sources.
The COSC status bits are read-only bits that indicate the current oscillator source the device is
operating from. The COSC bits default to the Internal Fast RC Oscillator with Postscaler
(FRCDIV), configured for 4 MHz, on a Power-on Reset (POR) and Master Clear Reset (MCLR
).
A clock switch will automatically be performed to the new oscillator source selected by the
FNOSC Configuration bits (Configuration Word 2<10:8>). The COSC bits will change to indicate
the new oscillator source at the end of a clock switch operation.
The NOSC status bits select the clock source for the next clock switch operation. On POR and
MCLR
s, these bits automatically select the oscillator source defined by the FNOSC Configuration
bits. These bits can be modified by software.
Setting the CLKLOCK bit (OSCCON<7>) prevents clock switching if the FCKSM1 Configuration
bit is set. If the FCKSM1 bit is clear, the CLKLOCK bit state is ignored and clock switching can
occur.
The IOLOCK bit (OSCCON<6>) is used to unlock the Peripheral Pin Select (PPS) feature; it has
no function in the system clock’s operation.
The LOCK status bit (OSCCON<5>) is read-only and indicates the status of the PLL circuit. It is
set when the PLL achieves a frequency lock and is RESET when a valid clock switching
sequence is initiated. It reads as ‘0’ whenever the PLL is not used as part of the current clock
source.
The CF status bit (OSCCON<3>) is a readable/clearable status bit that indicates a clock failure;
it is reset whenever a valid clock switch occurs.
The POSCEN bit (OSCCON<2>) is used to control the operation of the Primary Oscillator in
Sleep mode. Setting this bit bypasses the normal automatic shutdown of the oscillator whenever
Sleep mode is invoked.
The SOSCEN control bit (OSCCON<1>) is used to enable or disable the 32 kHz crystal SOSC
Oscillator.
The OSWEN control bit (OSCCON<0>) is used to initiate a clock switch operation. OSWEN is
cleared automatically after a successful clock switch, any redundant clock switch and by the
FSCM module after the switch to the FRC has completed.
Note: An unlock sequence must be performed before writing to OSCCON. Refer to
Section 6.11.2 “Oscillator Switching Sequence” for more information.

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