# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004

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 2010-2013 Microchip Technology Inc. DS39881E-page 37
TABLE 4-10: UART REGISTER MAP
File
Name
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
U1MODE 0220 UARTEN
 USIDL IREN RTSMD  UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL
U1STA 0222 UTXISEL1 UTXINV UTXISEL0
 UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR
U1TXREG 0224
       UTX8 UTX7 UTX6 UTX5 UTX4 UTX3 UTX2
U1RXREG 0226
       URX8 URX7 URX6 URX5 URX4 URX3 URX2
U1BRG 0228 Baud Rate Generator Prescaler Register
U2MODE 0230 UARTEN
 USIDL IREN RTSMD  UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL
U2STA 0232 UTXISEL1 UTXINV UTXISEL0
 UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR
U2TXREG 0234
       UTX8 UTX7 UTX6 UTX5 UTX4 UTX3 UTX2
U2RXREG 0236
       URX8 URX7 URX6 URX5 URX4 URX3 URX2
U2BRG 0238 Baud Rate Generator Prescaler
Legend:  = unimplemented, read as 0. Reset values are shown in hexadecimal.
TABLE 4-11: SPI REGISTER MAP
File
Name
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
SPI1STAT 0240 SPIEN
 SPISIDL   SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0
SPI1CON1 0242
   DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0
SPI1CON2 0244 FRMEN SPIFSD SPIFPOL
          
SPI1BUF 0248 SPI1 Transmit/Receive Buffer
SPI2STAT 0260 SPIEN
 SPISIDL   SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0
SPI2CON1 0262
   DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0
SPI2CON2 0264 FRMEN SPIFSD SPIFPOL
          
SPI2BUF 0268 SPI2 Transmit/Receive Buffer
Legend:  = unimplemented, read as 0. Reset values are shown in hexadecimal.

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