# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Reset

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PIC24F Family Reference Manual
DS39712D-page 7-14 © 2011 Microchip Technology Inc.
7.13.1 VBAT/Deep Sleep Status Bit Decoding
There are several unique Reset settings involving V BAT, VBPOR and DPSLP with regard to the
device’s Power-on Reset (POR), as indicated in Table 7-3.
7.13.2 Using the RCON Status Bits
The user can read the RCON register after any device Reset to determine the cause of the Reset.
Table 7-4 provides a summary of the Reset flag bit operation.
Table 7-4: Reset Flag Bit Operation
Table 7-3: V
BAT and Reset Flag Bit Operation
Flag Bit Set By Cleared By
VDDBOR (RCON2<3>) POR, BOR —
VDDPOR (RCON2<2>) POR on V
DD pin —
VBPOR (RCON2<1>) Battery failure in VBAT mode —
VBAT (RCON<1>) POR with V
BAT —
Note: The status bits in the RCON register should be cleared after they are read so that
the next RCON register value, after a device Reset, will be meaningful.
Flag Bit
(1)
Set By Cleared By
TRAPR (RCON<15>) Trap Conflict Event POR
IOPWR (RCON<14>) Illegal Opcode or Uninitialized
W Register Access
POR
DPSLP (RCON<10>)
(2)
Deep Sleep Sequence
(set DSEN, then execute
PWRSAV #SLEEP instruction)
POR
EXTR (RCON<7>) MCLR
Reset POR
SWR (RCON<6>) RESET Instruction POR
WDTO (RCON<4>) WDT Time-out PWRSAV Instruction, POR
SLEEP (RCON<3>)
(1)
PWRSAV #SLEEP Instruction POR, CLRWDT instruction
IDLE (RCON<2>)
(1)
PWRSAV #IDLE Instruction POR, CLRWDT instruction
BOR (RCON<1>) POR, BOR —
POR (RCON<0>) POR on V
DDCORE —
Note 1: All Reset flag bits may be set or cleared by the user software. Setting a Reset flag
does not trigger the associated Reset state.
2: This bit is only available on select PIC24F devices.

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