# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Family Data Sheet

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PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
DS39997C-page 24 Preliminary © 2011-2012 Microchip Technology Inc.
2.7 Oscillator Value Conditions on
Device Start-up
If the PLL of the target device is enabled and
configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to 4 MHz < F
IN < 8 MHz (for MSPLL mode) or 3 MHz <
FIN < 8 MHz (for ECPLL mode) to comply with device
PLL start-up conditions. HSPLL mode is not supported.
This means that if the external oscillator frequency is
outside this range, the application must start-up in the
FRC mode first. The fixed PLL settings of 4x after a
POR with an oscillator frequency outside this range will
violate the device operating speed.
Once the device powers up, the application firmware
can enable the PLL, and then perform a clock switch to
the Oscillator + PLL clock source. Note that clock
switching must be enabled in the device Configuration
word.
2.8 Configuration of Analog and
Digital Pins During ICSP
Operations
If MPLAB ICD 3 or MPLAB REAL ICE in-circuit
emulator is selected as a debugger, it automatically
initializes all of the analog-to-digital input pins (ANx) as
“digital” pins, by setting all bits in the AD1PCFGL
register.
The bits in the register that correspond to the
analog-to-digital pins that are initialized by MPLAB
ICD 3 or MPLAB REAL ICE in-circuit emulator, must
not be cleared by the user application firmware;
otherwise, communication errors will result between
the debugger and the device.
If your application needs to use certain analog-to-digital
pins as analog input pins during the debug session, the
user application must clear the corresponding bits in
the AD1PCFGL register during initialization of the ADC
module.
When MPLAB ICD 3 or MPLAB REAL ICE in-circuit
emulator is used as a programmer, the user application
firmware must correctly configure the AD1PCFGL
register. Automatic initialization of this register is only
done during debugger operation. Failure to correctly
configure the register(s) will result in all
analog-to-digital pins being recognized as analog input
pins, resulting in the port value being read as a logic ‘0’,
which may affect user application functionality.
2.9 Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic-low state.
Alternately, connect a 1k to 10k resistor between V
SS
and unused pins.

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