# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Power Saving Features

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© 2006 Microchip Technology Inc. Advance Information DS39698A-page 10-3
Section 10. Power-Saving Features
Power-Saving
Features
10
10.3.1 Sleep Mode
The characteristics of Sleep mode are as follows:
• The system clock source is shut down. If an on-chip oscillator is used, it is turned off.
• The device current consumption will be at a minimum, provided that no I/O pin is sourcing
current.
• The Fail-Safe Clock Monitor (FSCM) does not operate during Sleep mode since the system
clock source is disabled.
• The LPRC clock will continue to run in Sleep mode if the WDT is enabled.
• If the on-chip voltage regulator is enabled, its BOR circuit remains operative during Sleep
mode.
• The WDT, if enabled, is automatically cleared prior to entering Sleep mode.
• Some peripherals may continue to operate in Sleep mode. These peripherals include I/O
pins that detect a change in the input signal, or peripherals that use an external clock input.
Any peripheral that operates from the system clock source will be disabled in Sleep mode.
The processor will exit, or ‘wake-up’, from Sleep on one of the following events:
• On any interrupt source that is individually enabled
• On any form of device Reset
• On a WDT time-out
10.3.1.1 CLOCK SELECTION ON WAKE-UP FROM SLEEP
The processor will restart the same clock source that was active when Sleep mode was entered.
10.3.1.2 DELAY ON WAKE-UP FROM SLEEP
The restart delay associated with waking up from Sleep mode for different oscillator modes is
shown in Table 10-1.
Table 10-1: Delay Times for Exit from Sleep Mode
Clock Source
Sleep Exit
Delay
Oscillator Delay
FSCM
Delay
Notes
EC T
VREG — — 1
ECPLL TVREG TLOCK TFSCM 1, 3, 4
XT, HS T
VREG T OST TFSCM 1, 2, 4
XTPLL TVREG T OST + TLOCK TFSCM 1, 2, 3, 4
HSPLL TVREG T OST + TLOCK TFSCM 1, 2, 3, 4, 5
SOSC (Off during Sleep) T
VREG T OST TFSCM 1, 2, 4
(On during Sleep) TVREG — — 1
FRC, FRCDIV, LPRC T
VREG — — 1
FRCPLL T
VREG TLOCK — 1, 3
Note 1: TVREG = Start-up delay, only if on-chip regulator is enabled (10 μs nominal).
2: T
OST = Oscillator Start-up Timer; a delay of 1024 oscillator periods before the
oscillator clock is released to the system.
3: T
LOCK = PLL lock time (20 ms nominal).
4: T
FSCM = Fail-Safe Clock Monitor delay (100 μs nominal) if FSCM is enabled.
5: HSPLL mode exceeds PIC24F maximum operating frequency.
Note: Please refer to the “Electrical Characteristics” section of the product data sheet
for maximum operating frequency, T
VREG, TFSCM and TLOCK specification values.

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