# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Interrupts

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PIC24F Family Reference Manual
DS39707A-page 8-12 Advance Information © 2006 Microchip Technology Inc.
8.4 INTERRUPT CONTROL AND STATUS REGISTERS
The following registers are associated with the interrupt controller:
• INTCON1, INTCON2 Registers
Global interrupt control functions are derived from these two registers. INTCON1 contains the
Interrupt Nesting Disable (NSTDIS) bit, as well as the control and status flags for the
processor trap sources. The INTCON2 register controls the external interrupt request signal
behavior and the use of the alternate vector table.
• IFSn: Interrupt Flag Status Registers
All interrupt request flags are maintained in the IFSn registers, where ‘n’ denotes the register
number. Each source of interrupt has a status bit, which is set by the respective peripherals or
external signal, and is cleared via software.
• IECn: Interrupt Enable Control Registers
All interrupt enable control bits are maintained in the IECn registers, where ‘n’ denotes the
register number. These control bits are used to individually enable interrupts from the
peripherals or external signals.
• IPCn: Interrupt Priority Control Registers
Each user interrupt source can be assigned to one of eight priority levels. The IPCn registers
are used to set the interrupt priority level for each source of interrupt.
• SR: CPU STATUS Register
The SR is not specifically part of the interrupt controller hardware, but it contains the IPL<2:0>
status bits (SR<7:5>) that indicate the current CPU priority level. The user may change the
current CPU priority level by writing to the IPL bits.
• CORCON: Core Control Register
The CORCON is not specifically part of the interrupt controller hardware, but it contains the
IPL3 status bit which indicates the current CPU priority level. IPL3 is a read-only bit, so that
trap events cannot be masked by the user software.
SR, CORCON, INTCON1 and INTCON2 registers are described in details on the following
pages. The generic interrupt registers map is also given on the following pages. Each interrupt
is associated with an Interrupt Flag (IF), an Interrupt Enable bit (IE) and three Interrupt Priority
Bits (IP2:IP0). Actual number of IFSn, IECn and IPCn registers depends upon the number of
interrupts implemented on a particular device. Refer to the specific data sheet for further details.
8.4.1 Assignment of Interrupts to Control Registers
The interrupt sources are assigned to the IFSn, IECn and IPCn registers in a particular
sequence. For example, Interrupt Vector 0 has a natural order priority of 0. Thus, the Interrupt
Vector 0 status bit is found in IFS0<0>. Interrupt Vector 0 uses IEC0<0> as its enable bit and the
IPC0<2:0> bits assign the interrupt priority level for Interrupt Vector 0. Refer to Table 8-2 for a
generic summary of all the interrupt related registers.

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