# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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dsPIC33/PIC24 Family Reference Manual
DS70000195F-page 56  2007-2014 Microchip Technology Inc.
7.5 Sending Data to a Master Device
When the R/W status bit of the incoming device address byte is ‘1’ and an address match occurs,
the R/W
status bit (I2CxSTAT<2>) is set. At this point, the master device is expecting the slave
to respond by sending a byte of data. The contents of the byte are defined by the system protocol
and are only transmitted by the slave.
When the interrupt from the address detection occurs, the user software can write a byte to the
I2CxTRN register to start the data transmission.
The slave sets the TBF status bit (I2CxSTAT<0>). The eight data bits are shifted out on the falling
edge of the SCLx input. This ensures that the SDAx signal is valid during the SCLx high time.
When all 8 bits have been shifted out, the TBF status bit is cleared.
The slave detects the Acknowledge from the master-receiver on the rising edge of the ninth SCLx
clock.
If the SDAx line is low, indicating an ACK
, the master is expecting more data and the message
is not complete. The module generates a slave interrupt and the ACKSTAT status bit
(I2CxSTAT<15>) can be inspected to determine whether more data is being requested.
A slave interrupt is generated on the falling edge of the ninth SCLx clock. User software must
check the status of the I2CxSTAT register and clear the SI2CxIF interrupt flag.
If the SDAx line is high, indicating a NACK, the data transfer is complete. The slave resets and
generates an interrupt and it waits for detection of the next Start bit.
7.5.1 WAIT STATES DURING SLAVE TRANSMISSIONS
During a slave transmission message, the master expects return data immediately after
detection of the valid address with R/W
= 1. Because of this, the slave automatically generates
a bus Wait whenever the slave returns data.
The automatic Wait occurs at the falling edge of the ninth SCLx clock of a valid device address byte,
or transmitted byte, Acknowledged by the master, indicating expectation of more transmit data.
The slave clears the SCLREL bit (I2CxCON<12> or I2CxCONL<12>). Clearing the SCLREL bit
causes the slave to pull the SCLx line low, initiating a Wait. The SCLx clock of the master and
slave will synchronize, as shown in Section 6.2 “Master Clock Synchronization”.
When the user software loads the I2CxTRN register and is ready to resume transmission, the
user software sets the SCLREL bit. This causes the slave to release the SCLx line and the
master resumes clocking.
Note: When the IPMIEN bit (I2CxCON<11>) is equal to ‘1’ (IPMI mode), the I
2
C module
assumes that the R/W
bit is ‘0’. Therefore, the slave transmission function is
disabled. If the R/W
bit is ‘1’, the I
2
C module will trigger an interrupt. This interrupt
should be ignored (that is, the I
2
C interrupt flags should be cleared) and the I
2
C
slave transmission event should be aborted.
Note: The user software must provide a delay between writing to the transmit buffer and
setting the SCLREL bit. This delay must be greater than the minimum set up time
for slave transmissions, as specified in the “Electrical Characteristics” chapter of
the specific device data sheet.

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