# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- High-Level Device Integration

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PIC24F Family Reference Manual
DS39719D-page 32-8 © 2010 Microchip Technology Inc.
When the device enters Tracking mode, it is no longer possible to operate at full speed. To
provide information on when the device enters Tracking mode, the on-chip regulator includes a
simple, Low-Voltage Detect circuit. When V DD drops below full-speed operating voltage, the
circuit sets the Low-Voltage Detect Interrupt Flag, LVDIF. This can be used to generate an
interrupt and put the application into a low-power operational mode or trigger an orderly
shutdown. Low-Voltage Detection is only available when the regulator is enabled. If V
DD drops
below minimum Tracking mode voltage, a Brown-out Reset will be generated. Refer to the
Electrical Characteristics section of the specific device data sheet to find the LVD trip point and
the BOR trip point.
Figure 32-1: Connections for On-Chip Regulator (Positive Enable and Positive Disable)
VDD
ENVREG
V
DDCORE/VCAP
VSS
PIC24F
3.3V
(1)
2.5V
(1)
VDD
ENVREG
V
DDCORE/VCAP
VSS
PIC24F
CEFC
3.3V
Regulator Enabled (ENVREG tied to V DD):
Regulator Disabled (ENVREG tied to ground):
VDD
ENVREG
V
DDCORE/VCAP
VSS
PIC24F
2.5V
(1)
Regulator Disabled (VDD tied to VDDCORE):
Note 1: These are typical operating voltages. Refer to the Electrical Characteristics in the specific device data
sheet for the full operating ranges of V
DD and VDDCORE.
(10 F typ)
VDD
DISVREG
V
DDCORE/VCAP
VSS
PIC24F
3.3V
(1)
2.5V
(1)
Regulator Disabled (DISVREG tied to V DD):
VDD
DISVREG
V
DDCORE/VCAP
VSS
PIC24F
2.5V
(1)
Regulator Disabled (V DD tied to VDDCORE):
VDD
DISVREG
V
DDCORE/VCAP
VSS
PIC24F
CEFC
3.3V
(10 F typ)
Regulator Enabled (DISVREG tied to V
SS):
Positive Enable (ENVREG) Devices
Positive Disable (DISVREG) Devices

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