# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Interrupts

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© 2006 Microchip Technology Inc. Advance Information DS39707A-page 8-17
Section 8. Interrupts
Interrupts
8
Register 8-7: IECn: Interrupt Enable Registers 0 Through 6 (Interrupt Vectors 0 Through 111)
(1
)
Register 8-8: IECn: Interrupt Enable Register 7 (Interrupt Vectors 112 Through 117)
(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
V(16n + 15)IE V(16n + 14)IE V(16n + 13)IE V(16n + 12)IE V(16n + 11)IE V(16n + 10)IE V(16n + 9)IE V(16n + 8)IE
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
V(16n + 7)IE V(16n + 6)IE V(16n + 5)IE V(16n + 4)IE V(16n + 3)IE V(16n + 2)IE V(16n + 1)IE V(16n + 0)IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at any Reset ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 V(16n + x)IF: Interrupt Enable bits for Interrupt Vector 16n + x (where x = bit position number)
1 = Interrupt is enabled
0 = Interrupt is disabled
Note 1: Not all interrupt vectors are implemented on all devices. Refer to the Interrupt Vector Table for the specific
device or family data sheet to verify where interrupt vectors are implemented for a specific device.
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — V117IF V116IF V115IF V114IF V113IF V112IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at any Reset ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-6 Unimplemented: Read as ‘0’
bit 5-0 V117IE:V112IE Interrupt Enable bits for Interrupt Vectors 117 through 112
1 = Interrupt is enabled
0 = Interrupt is disabled
Note 1: Not all interrupt vectors are implemented on all devices. Refer to the Interrupt Vector Table for the specific
device or family data sheet to verify where interrupt vectors are implemented for a specific device.

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