# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004

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 2010-2013 Microchip Technology Inc. DS39881E-page 153
PIC24FJ64GA004 FAMILY
16.3 Setting Baud Rate When
Operating as a Bus Master
To compute the Baud Rate Generator reload value, use
Equation 16-1.
EQUATION 16-1: COMPUTING BAUD RATE
RELOAD VALUE
(1)
16.4 Slave Address Masking
The I2CxMSK register (Register 16-3) designates
address bit positions as dont care for both 7-Bit and
10-Bit Addressing modes. Setting a particular bit loca-
tion (= 1) in the I2CxMSK register causes the slave
module to respond whether the corresponding address
bit value is a 0 or a 1. For example, when I2CxMSK
is set to 00100000, the slave module will detect both
addresses, 00000000 and 00100000.
To enable address masking, the IPMI (Intelligent
Peripheral Management Interface) must be disabled by
clearing the IPMIEN bit (I2CxCON<11>).
TABLE 16-1: I
2
C™ CLOCK RATES
(1)
TABLE 16-2: I
2
C™ RESERVED ADDRESSES
(1)
I2CxBRG
F
CY
FSCL
------------
F
CY
10 000 000 
------------------------------–
 
 
1–=
F
SCL
FCY
I2CxBRG 1
F
CY
10 000 000 
------------------------------+ +
----------------------------------------------------------------------=
or
Note 1: Based on F
CY = FOSC/2; Doze mode
and PLL are disabled.
Note: As a result of changes in the I
2
C proto-
col, the addresses in Table 16-2 are
reserved and will not be Acknowledged in
Slave mode. This includes any address
mask settings that include any of these
addresses.
Required
System
F
SCL
FCY
I2CxBRG Value
Actual
FSCL
(Decimal) (Hexadecimal)
100 kHz 16 MHz 157 9D 100 kHz
100 kHz 8 MHz 78 4E 100 kHz
100 kHz 4 MHz 39 27 99 kHz
400 kHz 16 MHz 37 25 404 kHz
400 kHz 8 MHz 18 12 404 kHz
400 kHz 4 MHz 9 9 385 kHz
400 kHz 2 MHz 4 4 385 kHz
1 MHz 16 MHz 13 D 1.026 MHz
1 MHz 8 MHz 6 6 1.026 MHz
1 MHz 4 MHz 3 3 0.909 MHz
Note 1: Based on F
CY = FOSC/2; Doze mode and PLL are disabled.
Slave
Address
R/W
Bit
Description
0000 000 0 General Call Address
(2)
0000 000 1 Start Byte
0000 001 x Cbus Address
0000 010 x Reserved
0000 011 x Reserved
0000 1xx x HS Mode Master Code
1111 1xx x Reserved
1111 0xx x 10-Bit Slave Upper Byte
(3)
Note 1: The address bits listed here will never cause an address match, independent of the address mask settings.
2: The address will be Acknowledged only if GCEN = 1.
3: A match on this address can only occur on the upper byte in 10-Bit Addressing mode.

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