# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004

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DS39881E-page 42  2010-2013 Microchip Technology Inc.
TABLE 4-22: CLOCK CONTROL REGISTER MAP
File
Name
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
RCON 0740 TRAPR IOPUWR
    CM PMSLP EXTR SWR SWDTEN WDTO SLEEP IDLE
OSCCON 0742
 COSC2 COSC1 COSC0  NOSC2 NOSC1 NOSC0 CLKLOCK IOLOCK LOCK  CF 
CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 DOZEN RCDIV2 RCDIV1 RCDIV0
     
OSCTUN 0748
          TUN5 TUN4 TUN3 TUN2
Legend:  = unimplemented, read as 0. Reset values are shown in hexadecimal.
Note 1: RCON register Reset values are dependent on the type of Reset.
2: OSCCON register Reset values are dependent on configuration fuses and by the type of Reset.
TABLE 4-23: NVM REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
NVMCON 0760 WR WREN WRERR
      ERASE   NVMOP3 NVMOP
NVMKEY 0766         NVMKEY<7:0>
Legend:  = unimplemented, read as 0. Reset values are shown in hexadecimal.
Note 1: Reset value shown is for a POR only. The value on other Reset states is dependent on the state of the memory write or erase operations at the time of Reset.
TABLE 4-24: PMD REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 B
PMD1 0770 T5MD T4MD T3MD T2MD T1MD
   I2C1MD U2MD U1MD SPI2MD SPI1MD 
PMD2 0772
   IC5MD IC4MD IC3MD IC2MD IC1MD    OC5MD OC4MD OC3MD
PMD3 0774
     CMPMD RTCCMD PMPMD CRCPMD      I
Legend:  = unimplemented, read as 0. Reset values are shown in hexadecimal.

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