# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Serial Peripheral Interface

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© 2007 Microchip Technology Inc. Advance Information DS39699B-page 23-24
Section 23. Serial Peripheral Interface (SPI)
Serial Peripheral
Interface (SPI)
23
23.5 OPERATION IN POWER-SAVING MODES
The PIC24 family of devices has three Power modes: the normal Operational (Full-Power) mode,
and the two Power-Saving modes, invoked by the PWRSAV instruction. Depending on the SPI
mode selected, entering a Power-Saving mode may also affect the operation of the module.
23.5.1 Sleep Mode
When the device enters Sleep mode, the system clock is disabled. The consequences of enter-
ing Sleep depend on which mode (Master or Slave) the module is configured in at the time that
Sleep mode is invoked.
23.5.1.1 MASTER MODE OPERATION
The following are a consequence of entering Sleep mode when the SPIx module is configured
for master operation:
• The Baud Rate Generator in the SPIx module stops and is reset.
• The transmitter and receiver will stop in Sleep. The transmitter or receiver will not continue
with a partially completed transmission at wake-up.
• If the SPIx module enters Sleep mode in the middle of a transmission or reception, the trans-
mission or reception is aborted. Since there is no automatic way to prevent an entry into
Sleep mode if a transmission or reception is pending, the user software must synchronize
entry into Sleep with the SPIx module operation to avoid aborted transmissions.
23.5.1.2 SLAVE MODE OPERATION
Since the clock pulses at SCKx are externally provided for Slave mode, the module will continue
to function in Sleep mode. It will complete any transactions during the transition into Sleep. On
completion of a transaction, the SPIxRBF flag is set. Consequently, the SPIxIF bit will be set. If
SPIx interrupts are enabled (SPIxIE = 1), the device will wake from Sleep. If the SPIx interrupt
priority level is greater than the present CPU priority level, code execution will resume at the SPIx
interrupt vector location. Otherwise, code execution will continue with the instruction following the
PWRSAV instruction that previously invoked Sleep mode. The module is not reset on entering
Sleep mode if it is operating as a slave device.
Register contents are not affected when the SPIx module is going into or coming out of Sleep
mode.
23.5.2 Idle Mode
When the device enters Idle mode, the system clock sources remain functional. The SPISIDL bit
(SPIxSTAT<13>) selects whether the module will stop or continue functioning on Idle.
If SPISIDL = 1, the SPIx module will stop communication on entering Idle mode. It will operate
in the same manner as it does in Sleep mode. If SPISIDL = 0 (default selection), the module will
continue operation in Idle mode.

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