# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Comparator with Blanking

- 1
- 2
…
- 15
- 16
- 17
- 18
- 19
…
- 29
- 30

© 2010 Microchip Technology Inc. Preliminary DS39741A-page 48-17
Section 48. Comparator with Blanking
Comparator with
Blanking
48
48.4.4 Comparator Polarity Selection
To provide maximum flexibility, the output of the comparator may be inverted using the CPOL bit
(CMxCON<13>). This is functionally identical to reversing the inverting and non-inverting inputs
of the comparator for a particular mode.
The CPOL bit (CMxCON<13>) should be changed only when the comparator is disabled
(CON = 0). Internal logic will prevent the generation of any corresponding triggers or interrupts
when CON = 0. The logic allows both the CON and CPOL bits to be set with a single register
write.
48.4.5 Event Polarity Selection
In addition to a programmable comparator output polarity, the Comparator with Blanking module
also allows software selection for trigger/interrupt edge polarity through the EVPOL<1:0> bits
(CMxCON<7:6>). This feature allows independent control of the comparator output, as seen on
any external pins, and the trigger/interrupt generation.
48.4.6 Comparator Reference Input Selection
The input to the non-inverting input of the comparator, also known as the reference input, can be
selected between the following settings:
• CxINA pin (CON = 1, CREF = 0)
• Internal CV REF voltage (CON = 1, CREF = 1)
48.4.7 Comparator Channel Selection
The input to the inverting input of the comparator, also known as the channel input, can be
selected between the following settings:
• CxINB pin (CON = 1, CCH<1:0> = ‘b00)
• CxINC pin (CON = 1, CCH<1:0> = ‘b01)
• CxIND pin (CON = 1, CCH<1:0> = ‘b10)
• Band Gap Reference (CON = 1, CCH<1:0> = ‘b11). The source of the band gap
reference can be selected by the user-assigned application through the BGSEL<1:0> bits
(CVRCON<9:8>).
48.4.8 Low-Power Selection
Depending on the capabilities of the comparator modules, this interface provides a low-power
mode selection bit, CLPWR (CMxCON<12>). Using this bit, a user can trade-off power
consumption for the speed of the comparator.
When CLPWR = 0, the Standard Power mode is active. When CLPWR = 1, the low-power
setting of the corresponding comparator is enabled.
48.4.9 Comparator Event Status Bit
The Comparator Event Status (CEVT) bit (CMxCON<9>) reflects whether or not the comparator
has gone through the preconfigured event. After the bit is set, all future triggers and interrupts
from the corresponding comparator will be blocked until the user-assigned application clears the
CEVT bit. Clearing the CEVT bit begins rearming the trigger. Once the CEVT bit is cleared, it
takes an extra CPU cycle for the comparator triggers to be fully rearmed.
Note: The corresponding comparator must be enabled (CON = 1) for the specific
trigger/interrupt generation to be enabled.
Note: The comparator power setting should not be changed while CON = 1.

- 1
- 2
…
- 15
- 16
- 17
- 18
- 19
…
- 29
- 30