# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 -- Errata

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 2009-2013 Microchip Technology Inc. DS80000470H-page 5
PIC24FJ64GA004 FAMILY
Silicon Errata Issues
1. Module: JTAG
When the JTAG is disabled, the pull-up resistor on
the TDI pin (Pin 35/RA9) will stay enabled on the
44-pin variants of the device. This can cause the
device to draw extra current when asleep if the pin
is used as an input and held low.
Work around:
The pin will not draw extra current if any of the
following work around techniques are used:
• The pin is used as an output.
• The pin is driven high as an input.
• JTAG is enabled.
Affected Silicon Revisions
2. Module: Low-Voltage Detect (LVD)
The Low-Voltage Detect interrupt will not occur if
the device comes out of Reset in a low-voltage
state. To trigger an interrupt, the voltage must
decrease to a low-voltage range while the device
is running.
Work around
None.
Affected Silicon Revisions
3. Module: Core
If a clock failure occurs when the device is in Idle
mode, the oscillator failure trap does not vector to
the Trap Service Routine. Instead, the device will
simply wake-up from Idle mode and continue code
execution if the Fail-Safe Clock Monitor (FSCM) is
enabled.
Work around
Whenever the device wakes up from Idle (assuming
the FSCM is enabled), the user software should
check the status of the OSCFAIL bit (INTCON1<1>)
to determine whether a clock failure occurred, and
then perform an appropriate clock switch operation.
Affected Silicon Revisions
4. Module: Core
If a RAM read is performed on the instruction
immediately prior to enabling Doze mode, then an
extra read event will occur when Doze mode is
enabled. On most SFRs and on user RAM space,
this will have no visible effect. However, this can
cause registers which perform actions on reads,
such as auto-incrementing or decrementing a
pointer or removing data from a FIFO buffer, to
repeat that action, possibly resulting in lost data.
Work around
On the instruction prior to entering Doze mode, be
sure not to read a register which performs a sec-
ondary action. Examples of this would be UARTx
and SPIx FIFO buffers, and the RTCVAL registers.
The easiest way to ensure this does not occur is to
execute a NOP instruction before entering Doze
mode.
Affected Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (B8).
A3/
A4
B4 B5
B8
X
A3/
A4
B4 B5
B8
X
A3/
A4
B4 B5
B8
X
A3/
A4
B4 B5
B8
X

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