# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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© 2005-2011 Microchip Technology Inc. DS70157F-page 205
Section 5. Instruction Descriptions
Instruction
Descriptions
5
CPBLT
Signed Compare Wb with Wn, Branch if Less Than (Wb < Wn)
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X
Syntax: {label:} CPBLT{.B} Wb, Wn, Expr
Operands: Wb ∈ [W0 ... W15]
Wn ∈ [W0 ... W15]
Operation: (Wb) – (Wn)
If (Wb) = (Wn), [(PC+2) + 2 * Expr] → PC and NOP → Instruction Register
Status Affected: None
Encoding: 1110 0110 1www wBnn nnnn ssss
Description: Compare the contents of Wb with the contents of Wn by performing the
subtraction (Wb) – (Wn), but do not store the result. If (Wb) = (Wn), the
next instruction (fetched during the current instruction execution) is
discarded, the PC is recalculated based on the 6-bit signed offset specified
by Expr, and on the next cycle, a NOP is executed instead. If (Wb) ≠ (Wn),
the next instruction is executed as normal (branch is not taken).
The ‘w’ bits select the address of the Wb source register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘s’ bits select the address of the Wn source register.
The ‘n’ bits select the offset of the branch destination.
Note: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
Words: 1
Cycles: 1 (5 if branch taken)
Example 1:
002000 HERE: CPBLT.B W8, W9, BYPASS; If W8 < W9 (Byte mode),
002002 ADD W2, W3, W4; Perform branch to BYPASS
002004 . . .
002006 . . .
002008 BYPASS: . . .
00200A . . .
Before
Instruction
After
Instruction
PC 00 2000 PC 00 2008
W8 00FF W8 00FF
W9 26FE W9 26FE
SR 0000 SR 0008 (N = 1)

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