# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 24 © 2005-2011 Microchip Technology Inc.
2.17 CORE CONTROL REGISTER
For all MCU and DSC devices, the 16-bit CPU Core Control register (CORCON), is used to set
the configuration of the CPU. This register provides the ability to map program space into data
space.
In addition to setting CPU modes, the CORCON register contains status information about the
IPL<3> Status bit, which indicates if a trap exception is being processed.
Depending on the MCU and DSC family, one of the following CORCON registers is used:
• Register 2-4 for PIC24F and PIC24H devices
• Register 2-5 for PIC24E devices
• Register 2-6 for dsPIC30F and dsPIC33F devices
• Register 2-7 for dsPIC33E devices
2.17.1 dsPIC30F, dsPIC33F, and dsPIC33E Specific bits
In addition to setting CPU modes, the following features are available through the CORCON
register:
• Set the ACCA and ACCB saturation enable
• Set the Data Space Write Saturation mode
• Set the Accumulator Saturation and Rounding modes
• Set the Multiplier mode for DSP operations
• Terminate DO loops prematurely
• Provide status information about the DO loop nesting level (DL<2:0>)
• Select fixed or variable interrupt latency (dsPIC33E only)
2.17.1.1 PIC24E and dsPIC33E SPECIFIC BITS
A Status bit (SFA) is available that indicates whether the Stack Frame is active.
2.18 SHADOW REGISTERS
A shadow register is used as a temporary holding register and can transfer its contents to or from
the associated host register when instructed. Some of the registers in the programmer’s model
have a shadow register, which is utilized during the execution of a DO, POP.S, or PUSH.S
instruction. Shadow register usage is shown in
Table 2-2.
For dsPIC30F and dsPIC33F devices, since the DCOUNT, DOSTART and DOEND registers are
shadowed, the ability to nest DO loops without additional overhead is provided. Since all shadow
registers are one register deep, up to one level of DO loop nesting is possible. Further nesting of
DO loops is possible in software, with support provided by the DO Loop Nesting Level Status bits
(DL<2:0>) in the CORCON register (CORCON<10:8>).
Note: PIC24E and dsPIC33E devices do not have a PSV control bit, it has been replaced
by the SFA bit.
Note: The DO instruction is only available in dsPIC30F, dsPIC33F, and dsPIC33E devices.
Table 2-2: Automatic Shadow Register Usage
Location
DO
(1)
POP.S/PUSH.S
DCOUNT
(1)
Yes —
DOSTART
(1)
Yes —
DOEND
(1)
Yes —
STATUS Register – DC, N, OV, Z and C bits — Yes
W0-W3 — Yes
Note 1: The DO shadow registers are only available in dsPIC30F and dsPIC33F devices.
Note: All shadow registers are one register deep and not directly accessible. Additional
shadowing may be performed in software using the software stack.

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