# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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© 2005-2011 Microchip Technology Inc. DS70157F-page 99
Section 5. Instruction Descriptions
Instruction
Descriptions
5
5.4 INSTRUCTION DESCRIPTIONS
ADD
Add f to WREG
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} ADD{.B} f {,WREG}
Operands: f ∈ [0 ... 8191]
Operation: (f) + (WREG) → destination designated by D
Status Affected: DC, N, OV, Z, C
Encoding: 1011 0100 0BDf ffff ffff ffff
Description: Add the contents of the default working register WREG to the contents of
the file register, and place the result in the destination register. The
optional WREG operand determines the destination register. If WREG is
specified, the result is stored in WREG. If WREG is not specified, the
result is stored in the file register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.
Words: 1
Cycles:
1
(1)
Note 1:
In dsPIC33E and PIC24E devices, the listed cycle count does not apply to read and
read-modify-write operations on non-CPU Special Function Registers. For more
details, see
Note 3
in
Section 3.2.1 “Multi-Cycle Instructions”
.
Example 1:
ADD.B RAM100 ; Add WREG to RAM100 (Byte mode)
Before
Instruction
After
Instruction
WREG CC80 WREG CC80
RAM100 FFC0 RAM100 FF40
SR 0000 SR 0005 (OV, C = 1)
Example 2:
ADD RAM200, WREG ; Add RAM200 to WREG (Word mode)
Before
Instruction
After
Instruction
WREG CC80 WREG CC40
RAM200 FFC0 RAM200 FFC0
SR 0000 SR 0001 (C = 1)

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