# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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© 2005-2011 Microchip Technology Inc. DS70157F-page 117
Section 5. Instruction Descriptions
Instruction
Descriptions
5
ASR
Arithmetic Shift Right f
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} ASR{.B} f {,WREG}
Operands: f ∈ [0 ... 8191]
Operation: For byte operation:
(f<7>) → Dest<7>
(f<7>) → Dest<6>
(f<6:1>) → Dest<5:0>
(f<0>) → C
For word operation:
(f<15>) → Dest<15>
(f<15>) → Dest<14>
(f<14:1>) → Dest<13:0>
(f<0>) → C
Status Affected: N, Z, C
Encoding: 1101 0101 1BDf ffff ffff ffff
Description: Shift the contents of the file register one bit to the right and place the result
in the destination register. The Least Significant bit of the file register is
shifted into the Carry bit of the STATUS Register. After the shift is
performed, the result is sign-extended. The optional WREG operand
determines the destination register. If WREG is specified, the result is
stored in WREG. If WREG is not specified, the result is stored in the file
register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ’1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.
Words: 1
Cycles:
1
(1)
Note 1:
In dsPIC33E and PIC24E devices, the listed cycle count does not apply to read and
read-modify-write operations on non-CPU Special Function Registers. For more
details, see
Note 3
in
Section 3.2.1 “Multi-Cycle Instructions”
.
C

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