# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- 10-Bit ADC

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© 2010 Microchip Technology Inc. Preliminary DS39737A-page 49-23
Section 49. 10-Bit ADC with 4 Simultaneous Conversions
10-Bit ADC with
4 Simultaneous
Conversions
49
49.4.4 Sample and Conversion Operation (SMPI) Bits
The SMPI<3:0> bits are referred to as the Number of Samples Per Interrupt Select bits.
An interrupt can be generated at the end of each sample/convert sequence, or after multiple
sample/convert sequences, as determined by the value of the SMPI<3:0> bits. The number of
sample/convert sequences between interrupts can vary between 1 and 16. The total number of
conversion results between interrupts is the product of the number of channels per sample,
created by the CHPS<1:0> bits, and the value of the SMPI<3:0> bits. See Section 49.5 “ADC
Interrupt Generation” for the SMPI values for various sampling modes.
49.4.5 Conversion Trigger Sources
It is often desirable to synchronize the end of sampling and the start of conversion with some
other timed event. The ADC module can use one of the following sources as a conversion trigger:
• External Interrupt Trigger (INT0 only)
• Timer Interrupt Trigger
• Motor Control PWM Special Event Trigger (PIC24F Motor Control Devices Only)
49.4.5.1 EXTERNAL INTERRUPT TRIGGER (INT0 ONLY)
When SSRC<2:0> = 001, the A/D conversion is triggered by an active transition on the INT0 pin.
The INT0 pin can be programmed for either a rising edge input or a falling edge input.
49.4.5.2 TIMER INTERRUPT TRIGGER
This ADC Module Trigger mode is configured by setting SSRC<2:0> = 010. TMR3 can be used
to trigger the start of the A/D conversion when a match occurs between the 16-bit Timer Count
register (TMR3) and the 16-bit Timer Period register (PR3).
49.4.5.3 MOTOR CONTROL PWM SPECIAL EVENT TRIGGER
The PWM module has an event trigger that allows A/D conversions to be synchronized to the
PWM time base. When SSRC<2:0> = 011, the A/D sampling and conversion times occur at any
user programmable point within the PWM period. The Special Event Trigger allows the user to
minimize the delay between the time when the A/D conversion results are acquired and the time
when the duty cycle value is updated.
The application should set the ASAM bit in order to ensure that the ADC module has sampled
the input sufficiently before the next conversion trigger arrives.
49.4.6 Configuring Analog Port Pins
The Analog/Digital Pin Configuration register (ADxPCFGL) specifies the input condition of the
device pins used as analog inputs. Along with the Data Direction register (TRISx) in the Parallel
I/O Port module, these registers control the operation of the ADC pins.
A pin is configured as an analog input when the corresponding PCFGn bit (ADxPCFGL<n>) is
clear. The ADxPCFGL register is cleared at Reset, causing the ADC input pins to be configured
for analog input by default at Reset.
When configured for analog input, the associated port I/O digital input buffer is disabled so that
it does not consume current.
The port pins that are desired as analog inputs must have their corresponding TRIS bit set,
specifying the port input. If the I/O pin associated with an A/D input is configured as an output,
the TRIS bit is cleared and the digital output level (V
OH or V OL) of the port is converted. After a
device Reset, all TRIS bits are set.
A pin is configured as a digital I/O when the corresponding PCFGn bit is set. In this configuration,
the input to the analog multiplexer is connected to AV
SS.
Note 1: When the ADC Port register is read, any pin configured as an analog input reads
as a ‘0’.
2: Analog levels on any pin that is defined as a digital input may cause the input buffer
to consume current that is out of the device specification.

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