# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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© 2005-2011 Microchip Technology Inc. DS70157F-page 33
Section 2. Programmer’s Model
Programmer’s
Model
2
Register 2-6: CORCON: Core Control Register (dsPIC30F and dsPIC33F Devices)
U-0 U-0 U-0 R/W-0 R(0)/W-0 R-0 R-0 R-0
— — — US EDT
(1)
DL<2:0>
(2,3)
bit 15 bit 8
R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0
SATA SATB SATDW ACCSAT IPL3
(4,5)
PSV RND IF
bit 7 bit 0
Legend: C = Clearable bit R = Readable bit W = Writable bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
U = Unimplemented bit, read as ‘0’
bit 15-13 Unimplemented: Read as ‘0’
bit 12 US: Unsigned or Signed Multiplier Mode Select bit
1 = Unsigned mode enabled for DSP multiply operations
0 = Signed mode enabled for DSP multiply operations
bit 11 EDT: Early DO Loop Termination Control bit
(1)
1 = Terminate executing DO loop at end of current iteration
0 = No effect
bit 10-8 DL<2:0>: DO Loop Nesting Level Status bits
(2, 3)
111 = DO looping is nested at 7 levels
110 = DO looping is nested at 6 levels
110 = DO looping is nested at 5 levels
110 = DO looping is nested at 4 levels
011 = DO looping is nested at 3 levels
010 = DO looping is nested at 2 levels
001 = DO looping is active, but not nested (just 1 level)
000 = DO looping is not active
bit 7 SATA: ACCA Saturation Enable bit
1 = Accumulator A saturation enabled
0 = Accumulator A saturation disabled
bit 6 SATB: ACCB Saturation Enable bit
1 = Accumulator B saturation enabled
0 = Accumulator B saturation disabled
bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit
1 = Data space write saturation enabled
0 = Data space write saturation disabled
bit 4 ACCSAT: Accumulator Saturation Mode Select bit
1 = 9.31 saturation (Super Saturation)
0 = 1.31 saturation (Normal Saturation)
bit 3 IPL3: Interrupt Priority Level 3 Status bit
(4, 5)
1 = CPU Interrupt Priority Level is 8 or greater (trap exception activated)
0 = CPU Interrupt Priority Level is 7 or less (no trap exception activated)
bit 2 PSV: Program Space Visibility in Data Space Enable bit
1 = Program space visible in data space
0 = Program space not visible in data space
Note 1: This bit will always read ‘0’.
2: DL<2:1> are read-only.
3: The first two levels of DO loop nesting are handled by hardware.
4: This bit may be read or cleared, but not set.
5: This bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.

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