# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- CPU

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© 2006 Microchip Technology Inc. Advance Information DS39703A-page 2-21
Section 2. CPU
CPU
2
2.10.1.2 INTERRUPTING A REPEAT LOOP
A REPEAT instruction loop may be interrupted at any time.
The RA state is preserved on the stack during exception processing to allow the user to execute
further REPEAT loops from within any number of nested interrupts. After SRL is stacked, the RA
Status bit is cleared to restore normal execution flow within the ISR.
Returning into a REPEAT loop from an ISR using RETFIE requires no special handling.
Interrupts will prefetch the repeated instruction during the third cycle of the RETFIE. The
stacked RA bit will be restored when the SRL register is popped, and if set, the interrupted
REPEAT loop will be resumed.
2.10.1.2.1 Early Termination of a REPEAT Loop
An interrupted REPEAT loop can be terminated earlier than normal in the ISR by clearing the
RCOUNT register in software.
2.10.1.3 RESTRICTIONS ON THE REPEAT INSTRUCTION
Any instruction can immediately follow a REPEAT except for the following:
1. Program flow control instructions (any branch, compare and skip, subroutine calls,
returns, etc.).
2. Another REPEAT instruction.
3. DISI, ULNK, LNK, PWRSAV, RESET instructions.
4. MOV.D instruction.
Note: If a REPEAT loop has been interrupted and an ISR is being processed, the user must
stack the RCOUNT (Repeat Loop Counter) register prior to executing another
REPEAT instruction within an ISR.
Note: If REPEAT was used within an ISR, the user must unstack RCOUNT prior to executing
RETFIE.
Note: Should the repeated instruction (target instruction in the REPEAT loop) be accessing
data from Program Space (PS) using Program Space Visibility (PSV), the first time
it is executed after a return from an exception will require 2 instruction cycles. Similar
to the first iteration of a loop, timing limitations will not allow the first instruction to
access data residing in PS in a single instruction cycle.

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