# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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DS70000195F-page 58  2007-2014 Microchip Technology Inc.
Figure 7-15: Slave Message (Read Data from Slave: 7-Bit Address)
1 Slave recognizes Start event, S and P bits set/clear accordingly.
SCLx (Master)
SDAx (Master)
SCLx (Slave)
SDAx (Slave)
I2CxTRN
TBF
I2CxRCV
RBF
SI2CxIF
STREN
1 2 3 4 5 6 7 8
A1A0
9
A
D7D6D5D4D3D2D1
1 2 3 4 5 6 7 8 9
1 42
A
5 3 5 3
2
Slave receives address byte. Address matches. Slave generates interrupt.
3
User software writes I2CxTRN with response data. TBF = 1 indicates that buffer is full.
6 At the end of ninth clock, if the master has sent an ACK
8
Slave recognizes Stop event, S and P bits set/clear acc
Address byte is moved to I2CxRCV register and is read by user software to prevent
Writing I2CxTRN sets
D/A, indicating a data byte.
A6A5 A4A3 A2
S
P
I2COV
R/W
D/A
SCLREL
4 4
D7D6D5D4D3D2D1
1 2 3 4 5 6 7 8 9
A
D7D6D5D4D3
1 2 3 4 5
3 6 6
master clock.
4
User software sets SCLREL to release clock hold. Master resumes clocking and
slave transmits data byte.
5 After last bit, module clears TBF bit, indicating buffer is
to suspend clock. Slave generates interrupt.
7
At the end of ninth clock, if master sent a NACK, no more
Module does not suspend clock and will generate an int
buffer overflow. R/W = 1 to indicate read from slave. SCLREL = 0 to suspend
D0D0
R

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