# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- UART

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 2009-2013 Microchip Technology Inc. DS70000582E-page 19
UART
5.4 Transmission of Break Characters
A Break character transmit consists of a Start bit, followed by twelve bits of 0 and a Stop bit. A
Frame Break character is sent whenever the UTXBRK and UTXEN bits are set, while the
Transmit Shift Register is loaded with data. A dummy write to the UxTXREG register is necessary
to initiate the Break character transmission. Note that the data value written to the UxTXREG for
the Break character is ignored. The write simply serves the purpose of initiating the proper
sequence  all 0s will be transmitted.
The UTXBRK bit is automatically reset by hardware after the corresponding Stop bit is sent. This
allows the user application to preload the transmit FIFO with the next transmit byte, following the
Break character (typically, the Sync character in the LIN/J2602 specification).
The TRMT bit indicates when the Transmit Shift Register is empty or full, just as it does during
the normal transmission. See Figure 5-5 for the timing of the Break character sequence.
Figure 5-5: Send Break Character Sequence
5.4.1 BREAK AND SYNC TRANSMIT SEQUENCE
The following sequence sends a message frame header made up of a Break, followed by an
auto-baud Sync byte. This sequence is typical of a LIN/J2602 bus master.
1. Configure the UART for the desired mode.
2. Set the UTXEN and UTXBRK bits to transmit the Break character.
3. Load the UxTXREG with a dummy character to initiate transmission (value is ignored).
4. Write 0x55 to UxTXREG  loads the Sync character into the transmit FIFO.
After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character is now
transmitted.
Note: The user application should wait for the transmitter to be Idle (TRMT = 1) before set-
ting the UTXBRK bit. The UTXBRK bit overrides any other transmitter activity. If the
user application clears the TXBRK bit prior to sequence completion, unexpected
module behavior can result. Sending a Break character does not generate a
transmit interrupt.
Write to UxTXREG
Start bit bit 0 bit 1 bit 11 Stop bit
Break
UxTX
TRMT bit
UTXBRK Sampled Here
Auto-Cleared
UTXBRK bit
UxTXIF
BCLKx/16
(Shift Clock)
Dummy Write

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