# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Serial Peripheral Interface

- 1
- 2
- 3
- 4
- 5
- 6
- 7
…
- 31
- 32

PIC24F Family Reference Manual
DS39699B-page 23-5 Advance Information © 2007 Microchip Technology Inc.
Register 23-1: SPIxSTAT: SPIx Status Register
R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
SPIEN
— SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0
Bit 15 Bit 8
R-0 R/C-0; HS R/W-0 R/W-0 R/W-0 R/W-0 R-0; HS; HC R-0; HS; HC
SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPIxTBF SPIxRBF
Bit 7 Bit 0
Legend:
R = Readable bit W = Writable bit C = Clearable bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
HS = Set in Hardware bit HC = Cleared in Hardware bit U = Unimplemented bit, read as ‘0’
bit 15 SPIEN: SPIx Enable bit
1 = Enables module and configures SCKx, SDOx, SDIx and SSx
as serial port pins
0 = Disables module
bit 14 Unimplemented: Read as ‘0’
bit 13 SPISIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode.
0 = Continue module operation in Idle mode.
bit 12-11 Unimplemented: Read as ‘0’
bit 10-8 SPIBEC2:SPIBEC0: SPIx Buffer Element Count bits
Master mode:
Number of SPIx transfers pending.
Slave mode:
Number of SPIx transfers unread.
bit 7 SRMPT: Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode)
1 = SPIx Shift register is empty and ready to send or receive
0 = SPIx Shift register is not empty
bit 6 SPIROV: Receive Overflow Flag bit
1 = New byte/word is completely received; CPU has not read previous data in the SPIBUF register
0 = No overflow
bit 5 SRXMPT: Receive FIFO Empty bit (valid in Enhanced Buffer mode)
1 = RX FIFO is empty
0 = RX FIFO is not empty
bit 4-2 SISEL2:SISEL0: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)
111 = Interrupt when SPIx transmit buffer is full (SPIxTBF bit is set)
110 = Interrupt when last bit is shifted into SPIxSR, as a result, the TX FIFO is empty
101 = Interrupt when the last bit is shifted out of SPIxSR, now the transmit is complete
100 = Interrupt when one data is shifted into the SPIxSR, as a result, the TX FIFO has one open spot
011 = Interrupt when SPIx receive buffer is full (SPIxRBF bit set)
010 = Interrupt when SPIx receive buffer is 3/4 or more full
001 = Interrupt when data is available in receive buffer (SRMPT bit is set)
000 = Interrupt when the last data in the receive buffer is read, as a result, the buffer is empty (SRXMPT
bit set)

- 1
- 2
- 3
- 4
- 5
- 6
- 7
…
- 31
- 32