# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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 2007-2014 Microchip Technology Inc. DS70000195F-page 15
Inter-Integrated Circuit™ (I
2
C™)
bit 5 D/A: Data/Address bit (I
2
C Slave mode)
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was a device address
Hardware clears at device address match; hardware sets by reception of a slave byte or sets after the
transmission is complete and the TBF flag is cleared.
bit 4 P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Hardware sets or clears when Start, Repeated Start or Stop is detected.
bit 3 S: Start bit
1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Start bit was not detected last
Hardware sets or clears when Start, Repeated Start or Stop is detected.
bit 2 R/W: Read/Write Information bit (when operating as I
2
C slave)
1 = Read, data transfer is an output from the slave
0 = Write, data transfer is an input to the slave
Hardware sets or clears after reception of an I
2
C device address byte.
bit 1 RBF: Receive Buffer Full Status bit
1 = Receive completes; the I2CxRCV register is full
0 = Receive is not complete; the I2CxRCV register is empty
Hardware sets when the I2CxRCV register is written with a received byte; hardware clears when user
software reads the I2CxRCV register.
bit 0 TBF: Transmit Buffer Full Status bit
1 = Transmit is in progress; the I2CxTRN register is full
0 = Transmit completes; the I2CxTRN register is empty
Hardware sets when user software writes to the I2CxTRN register; hardware clears at completion of the
data transmission.
Register 3-4: I2CxSTAT: I2Cx Status Register (Continued)
Note 1: Refer to the specific device data sheet for availability of the ACKTIM bit.

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