# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Serial Peripheral Interface

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© 2007 Microchip Technology Inc. Advance Information DS39699B-page 23-16
Section 23. Serial Peripheral Interface (SPI)
Serial Peripheral
Interface (SPI)
23
23.3.3 Enhanced Buffer Master and Slave Modes
The operation of Enhanced Buffer Master and Slave modes is very similar to Standard Master
and Slave modes. The difference is that data can be thought of as moving from the Shift register
to a receive FIFO buffer and moving from the transmit FIFO buffer to the Shift register. The
relationships in Enhanced Buffer mode are shown in Figure 23-8.
Figure 23-8: SPIx Master/Slave Connection (Enhanced Buffer Modes)
23.3.3.1 ENHANCED BUFFER MASTER MODE
In Enhanced Buffer Master mode, the system clock is prescaled and then used as the serial
clock. The prescaling is based on the settings in the PPRE1:PPRE0 (SPIxCON1<1:0>) and
SPRE1:SPRE0 (SPIxCON1<4:2>) bits. The serial clock is output via the SCKx pin to slave
devices. Clock pulses are only generated when there is data to be transmitted. For further infor-
mation, refer to Section 23.4 “SPI Master Mode Clock Frequency”. The CKP and CKE bits
determine on which edge of the clock, data transmission occurs.
The CPU loads data to be transmitted into the transmit buffer by writing the SSPBUF register. An
SPIx transmission begins after the first buffer write. Up to eight pending transmissions can be
loaded. The number of pending transfers is indicated by the Buffer Element Count bits
SPIBEC2:SPIBEC0 (SPIxSTAT<2:0>).
In Master mode, this count reflects the number of transfers pending in the transmit buffer. In
Slave mode, it reflects the number of unread receptions in the receive buffer. If the Shift register
is empty, the first write will immediately load the Shift register, leaving 8 transmit buffer locations
available.
After an SPIx transfer completes, the receive buffer location is updated with the received data.
The CPU accesses the received data by reading the SSPBUF register. After each CPU read, the
SSPBUF points to the next buffer location. SPIx transfers continue until all pending data transfers
have completed.
Shift Register
(SPIxSR)
SDIx
SDOx
PROCESSOR 2
SCKx
SSx
Shift Register
(SPIxSR)
MSb
LSb
SDOx
SDIx
PROCESSOR 1
Serial Clock
SSEN (SPIxCON1<7>) = 1 and
Note 1: Using the SSx
pin in Slave mode of operation is optional.
2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers
are memory mapped to SPIxBUF.
SSx
SCKx
MSTEN (SPIxCON1<5> = 1 and
SPIx Buffer
(SPIxBUF)
SPIx Buffer
(SPIxBUF)
SPIBEN (SPIxCON2<0>) = 1 MSTEN (SPIxCON1<5>) = 0 and
SPIBEN (SPIxCON2<0> = 1
Transfer
Transfer
8-Level FIFO
Transmit Buffer
8-Level FIFO
Receive Buffer
MSb
LSb
Transfer
Transfer
8-Level FIFO
Transmit Buffer
8-Level FIFO
Receive Buffer
(SPIx Enhanced Buffer Master) (SPIx Enhanced Buffer Slave)

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