# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

- 1
- 2
…
- 25
- 26
- 27
- 28
- 29
…
- 501
- 502

© 2005-2011 Microchip Technology Inc. DS70157F-page 27
Section 2. Programmer’s Model
Programmer’s
Model
2
Register 2-2: SR: CPU STATUS Register (dsPIC30F and dsPIC33F Devices)
R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R-0 R/W-0
OA OB SA
(1,2)
SB
(1,2)
OAB SAB
(1,2,3)
DA
(4)
DC
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
IPL2
(5)
IPL1
(5)
IPL0
(5)
RA N OV Z C
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit C = Clearable bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 OA: Accumulator A Overflow bit
1 = Accumulator A overflowed
0 = Accumulator A has not overflowed
bit 14 OB: Accumulator B Overflow bit
1 = Accumulator B overflowed
0 = Accumulator B has not overflowed
bit 13 SA: Accumulator A Saturation bit
(1, 2)
1 = Accumulator A is saturated or has been saturated since this bit was last cleared
0 = Accumulator A is not saturated
bit 12 SB: Accumulator B Saturation bit
(1, 2)
1 = Accumulator B is saturated or has been saturated at since this bit was last cleared
0 = Accumulator B is not saturated
bit 11 OAB: OA || OB Combined Accumulator Overflow bit
1 = Accumulator A or B has overflowed
0 = Neither Accumulator A nor B has overflowed
bit 10 SAB: SA || SB Combined Accumulator bit
(1, 2, 3)
1 = Accumulator A or B is saturated or has been saturated since this bit was last cleared
0 = Neither Accumulator A nor B is saturated
bit 9 DA: DO Loop Active bit
(4)
1 = DO loop in progress
0 = DO loop not in progress
bit 8 DC: MCU ALU Half Carry bit
1 = A carry-out from the MSb of the lower nibble occurred
0 = No carry-out from the MSb of the lower nibble occurred
bit 7-5 IPL<2:0>: Interrupt Priority Level bits
(5)
111 = CPU Interrupt Priority Level is 7 (15). User interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
Note 1: This bit may be read or cleared, but not set.
2: Once this bit is set, it must be cleared manually by software.
3: Clearing this bit will clear SA and SB.
4: This bit is read-only.
5: The IPL<2:0> bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL, if IPL3 = 1.

- 1
- 2
…
- 25
- 26
- 27
- 28
- 29
…
- 501
- 502