# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Motor Control PWM

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PIC24F Family Reference Manual
DS39735A-page 47-22 Preliminary © 2010 Microchip Technology Inc.
47.7.3 Timer Direction Control
The timer direction control block determines the count direction. The PWM Time Base Count
Direction Status (PTDIR) bit in the PWM Time Base (PxTMR<15>) register is a read-only bit
that gives the present direction of the count. If the PTDIR bit is cleared, PxTMR is counting
upward, and if it is set, PxTMR is counting downward. The time base is enabled or disabled by
setting or clearing the PWM Time Base Timer Enable (PTEN) bit in the PWM Time Base
Control (PxTMR<15>) register. The PxTMR register is not cleared when the PTEN bit is
cleared in software.
47.7.4 Time Base Output Postscaler
The time base output postscaler is used to optionally select one of several possible options
(1:1 to 1:16, scaling inclusive) to postscale the timer output. The interrupt control logic decides
when to set the PWM Interrupt Flag, PWMxIF, for generating a PWM interrupt, depending on
the postscale value. The postscaler is useful when the PWM duty cycles need not be updated
every PWM cycle.
The time base output postscaler counter is cleared when any of the following occurs:
 A write to the PxTMR register
 A write to the PxTCON register
 A device Reset
The PxTMR register is not cleared when the PxTCON register is written.
47.7.5 PWM Time Period
The PxTPER register determines the counting period for the PxTMR register. The user
application must write a 15-bit value into the PWM Time Base Period Value (PxTPER) bits of
the PWM Time Base (PxTMR<14:0>) register. When the value of PxTMR<14:0> matches the
value of PxTPER<14:0>, the time base will either reset to zero or reverse the count direction
on the next clock input edge. The action taken depends on the operating mode of the time
base.
The time base period is double-buffered to allow run-time changes of the time period of the
PWM signal without any glitches. The PxTPER register serves as a buffer to the actual
register, which is not accessible by the user application. The PxTPER register contents are
loaded into the actual Time Base Period register at the following times:
 Free-Running and Single Event modes: when the PxTMR register is reset to zero after a
match with the PxTPER register.
 Up/Down Counting modes: when the PxTMR register is zero.
The value held in the PxTPER register is automatically loaded into the PWM Time Base Period
(PxTPER) register when the PWM time base is disabled (PTEN = 0). Figure 47-3 and
Figure 47-4 indicate the times when the contents of the PxTPER register are loaded into the
Time Base Period register.
Figure 47-3: PWM Period Buffer Updates in Free-Running Count Mode
Old PxTPER Value
New PxTPER Value
Period Value Loaded from PxTPER Buffer Register
New Value Written to PxTPER Buffer
PxTMR Value

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