# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 -- Errata

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PIC24FJ64GA004 FAMILY
DS80000470H-page 16  2009-2013 Microchip Technology Inc.
42. Module: Core (Code Protection)
When General Segment Code Protection has
been enabled (GCP Configuration bit is pro-
grammed), applications are unable to write to the
first 512 bytes of the program memory space
(0000h through 0200h). In applications that may
require the interrupt vectors to be changed during
run time, such as bootloaders, modifications to the
Interrupt Vector Tables (IVTs) will not be possible.
Work around
Create two new Interrupt Vector Tables, one each
for the IVT and AIVT, in an area of program space
beyond the affected region. Map the addresses in
the old vector tables to the new tables. These new
tables can then be modified as needed to the
actual addresses of the ISRs.
Affected Silicon Revisions
43. Module: SPI
SPIx operating in Enhanced Buffer mode
(SPIBEN = 1) may set the interrupt flag, SPIxIF,
before the last bit has been transmitted from the
Shift register. This issue only affects one of the
eight Interrupt modes, SISEL<2:0> = 101,
which generates an interrupt when the last bit
has shifted out of the Shift register, indicating the
transfer is complete. All other Interrupt modes in
Enhanced Buffer mode work as described in the
product data sheet.
Work around
Multiple work arounds are available. Select
another Buffer Interrupt mode using the
SISEL<2:0> bits in the SPIxSTAT register. A
comparable mode is to generate an interrupt
when the FIFO is empty, SISEL<2:0> = 110.
Another option is to monitor the SRMPT bit
(SPIxSTAT<7>) to determine when the Shift
register is empty.
Affected Silicon Revisions
44. Module: UART (IrDA
®
)
When IrDA reception is enabled
(UxMODE<12> = 1), the operation of the RXINV
bit (UxMODE<4>) is the opposite of its descrip-
tion in the device data sheet (DS39881E); that is,
setting the bit configures the module for a logic
high Idle state, and clearing the bit configures the
module for a logic low Idle state. Using the bit as
described in the data sheet may result in
reception errors.
Work around
Invert the state of the RXINV bit. If the Idle state of
the received signal is logic high, set RXINV = 1. If
the Idle state of the received signal is logic low,
clear RXINV.
Affected Silicon Revisions
45. Module: Core
Operations that immediately follow any manipula-
tions of the DOZE<2:0> or DOZEN bits
(CLKDIV<14:11>) may not execute properly. In
particular, for instructions that operate on an
SFR, data may not be read properly. Also, bits
automatically cleared in hardware may not be
cleared if the operation occurs during this interval.
Work around
Always insert a NOP instruction before and after
either of the following:
• Enabling or disabling Doze mode by setting
or clearing the DOZEN bit.
• Before or after changing the DOZE<2:0>
bits.
Affected Silicon Revisions
A3/
A4
B4 B5 B8
X
A3/
A4
B4 B5
B8
X X X
X
A3/
A4
B4 B5
B8
X
A3/
A4
B4 B5
B8
X X X
X

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