# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Family Data Sheet

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© 2011-2012 Microchip Technology Inc. Preliminary DS39997C-page 157
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
15.2 PWM Faults
The Motor Control PWM module incorporates up to two
fault inputs, FLTA1 and FLTB1. These fault inputs are
implemented with Class B safety features. These fea-
tures ensure that the PWM outputs enter a safe state
when either of the fault inputs is asserted.
The FLTA
and FLTB pins, when enabled and having
ownership of a pin, also enable a soft internal pull-down
resistor. The soft pull-down provides a safety feature by
automatically asserting the fault should a break occur
in the fault signal connection.
The implementation of internal pull-down resistors is
dependent on the device variant. Table 15-1 describes
which devices and pins implement the internal pull-
down resistors.
TABLE 15-1: INTERNAL PULL-DOWN
RESISTORS ON PWM FAULT
PINS
On devices without internal pull-downs on the Fault pin,
it is recommended to connect an external pull-down
resistor for Class B safety features.
15.2.1 PWM FAULTS AT RESET
During any reset event, the PWM module maintains
ownership of both PWM Fault pins. At reset, both faults
are enabled in latched mode to guarantee the fail-safe
power-up of the application. The application software
must clear both the PWM faults before enabling the
Motor Control PWM module.
The Fault condition must be cleared by the external cir-
cuitry driving the fault input pin high and clearing the
fault interrupt flag. After the fault pin condition has been
cleared, the PWM module restores the PWM output
signals on the next PWM period or half-period bound-
ary.
Refer to Section 47. “Motor Control PWM”
(DS39735), in the “PIC24F Family Reference Manual”
for more information on the PWM faults.
15.3 Write-protected Registers
On PIC24FJ16MC101/102 devices, write protection is
implemented for the PWMxCON1, PxFLTACON and
PxFLTBCON registers. The write protection feature
prevents any inadvertent writes to these registers. The
write protection feature can be controlled by the
PWMLOCK configuration bit in the FOSCSEL configu-
ration register. The default state of the write protection
feature is enabled (PWMLOCK = 1). The write protec-
tion feature can be disabled by configuring PWMLOCK
(FOSCSEL<6>) = 0.
The user application can gain access to these locked
registers either by configuring the PWMLOCK (FOSC-
SEL<6>) = 0, or by performing the unlock sequence. To
perform the unlock sequence, the user application
must write two consecutive values of (0xABCD and
0x4321) to the PWMxKEY register to perform the
unlock operation. The write access to the PWMxCON1,
PxFLTACON or PxFLTBCON registers must be the
next SFR access following the unlock process. There
can be no other SFR accesses during the unlock pro-
cess and subsequent write access.
To write to all registers, the PWMxCON1, PxFLTACON
and PxFLTBCON registers require three unlock
operations.
The correct unlocking sequence is described in
Example 15-1 and Example 15-2.
Device Fault Pin
Internal
Pull-down
Implemented?
PIC24FJXXMC101 FLTA1
No
PIC24FJXXMC102 FLTA1 Yes
FLTB1
Yes
PIC24FJ32MC104 FLTA1 Yes
FLTB1 Yes
Note: The number of PWM faults mapped to the
device pins depend on the specific
variant. Regardless of the variant, both
faults will be enabled during any reset
event. The application must clear both
FLTA1
and FLTB1 before enabling the
Motor Control PWM module. Refer to the
specific device pin diagrams to see which
fault pins are mapped to the device pins.

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