# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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dsPIC33/PIC24 Family Reference Manual
DS70000195F-page 6  2007-2014 Microchip Technology Inc.
2.2 Message Protocol
A typical I
2
C message is illustrated in Figure 2-3. In this example, the message will read a
specified byte from a 24LC256 I
2
C serial EEPROM. The dsPIC33/PIC24 device will act as the
master and the 24LC256 device will act as the slave.
Figure 2-3 illustrates the data as driven by the master device and the slave device, taking into
account that the combined SDAx line is a wired-AND of the master and slave data. The master
device controls and sequences the protocol. The slave device will only drive the bus at
specifically determined times.
Figure 2-3: A Typical I
2
C™ Message: Read of Serial EEPROM (Random Address Mode)
2.2.1 START MESSAGE
Each message is initiated with a Start condition and terminated with a Stop condition. The
number of data bytes transferred between the Start and Stop conditions is determined by the
master device. As defined by the system protocol, the bytes of the message may have special
meaning, such as the device address byte or the data byte.
2.2.2 ADDRESS SLAVE
In Figure 2-3, the first byte is the device address byte, which must be the first part of any I
2
C
message. It contains a device address and a R/W
status bit. Note that the R/W = 0 for this first
address byte, indicating that the master will be a transmitter and the slave will be a receiver.
2.2.3 SLAVE ACKNOWLEDGE
The receiving device is obliged to generate an Acknowledge signal, ACK, after the reception of
each byte. The master device must generate an extra SCLx clock, which is associated with this
Acknowledge bit.
2.2.4 MASTER TRANSMIT
The next two bytes, sent by the master to the slave, are data bytes that contain the location of
the requested EEPROM data byte. The slave must Acknowledge each of the data bytes.
2.2.5 REPEATED START
The slave EEPROM has the required address information that is required to return the requested
data byte to the master. However, the R/W
status bit from the first device address byte specifies
the master transmission and the slave reception. The direction of the bus must be reversed for
the slave to send data to the master.
To perform this function without ending the message, the master sends a Repeated Start. The
Repeated Start is followed with a device address byte containing the same device address as
before and with the R/W
= 1 to indicate the slave transmission and the master reception.
X
Bus
Master
SDAx
Start
Address
Byte
EEPROM Address
High Byte
EEPROM Address
Low Byte
Address
Byte
Data
Byte
S 1 0 1 0
A A A
0
2 1 0
R 1 0 1 0
A A A
1
2 1 0
P
Slave
SDAx
Activity
N
AAAA
Output
Output
Idle
R/W
ACK
ACK
ACK
Restart
ACK
NACK
Stop
Idle
R/W

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