# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- High-Level Device Integration

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© 2010 Microchip Technology Inc. DS39719D-page 32-7
Section 32. High-Level Device Integration
High-Level Device
Integration
32
32.4 ON-CHIP VOLTAGE REGULATION
The PIC24FJ family powers its core digital logic at a nominal 2.5V. This may create an issue for
designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system
design, all PIC24FJ family devices incorporate an on-chip regulator that allows the device to run
its core logic from V
DD.
PIC24FJ family devices use two different control systems to control the on-chip regulators. In
some devices, the regulator is enabled by supplying V DD to the control pin, while in some
devices, the regulator is disabled when the control pin is supplied with V
DD. If the regulator is
enabled when V
DD is supplied, the control pin is named ENVREG. If the regulator is disabled
when V
DD is supplied, the control pin is named DISVREG.
When enabled, the regulator draws power from the V
DD pins to provide power to the digital logic.
When disabled, power for the core logic must be supplied to the device on the V
DDCORE/VCAP pin.
This can be done by supplying separate V
DD and VDDCORE voltage to allow the I/O pins to run at
higher voltage levels (nominal 2.5V and 3.3V for V
DDCORE and VDD, respectively). If the higher
voltage is not required, the V
DDCORE/VCAP and VDD pins can be tied together to operate at a lower
nominal voltage. Refer to the device data sheet for device-specific voltage limitations.
If the regulator is enabled, a capacitor with a low, effective, series resistance (made of tantalum
or ceramic) must be connected to the V
DDCORE/VCAP pin. This helps maintain the stability of the
regulator. The recommended values for the filter capacitor
and its ESR (Equivalent Series
Resistance) are provided in the Electrical Characteristics section of the specific device data
sheet.
Possible configurations for both positive enable and positive disable regulators are provided in
Figure 32-1.
32.4.1 On-Chip Regulator and Power-on Reset (POR)
When the voltage regulator is enabled, it takes approximately 20 s for it to generate output from
the point where
VDD attains the stability. During this time, designated as T STARTUP, code execu-
tion is disabled. T
STARTUP is applied every time the device resumes operation after any Power-Down
modes and Sleep mode.
If the regulator is disabled, a separate Power-up Timer (PWRT) is automatically enabled. The
PWRT adds a fixed delay of 64 ms nominal delay at device start-up.
32.4.2 On-Chip Regulator and Brown-out Reset (BOR)
When the on-chip regulator is enabled, the PIC24F family devices also have a simple brown-out
capability. If the voltage supplied to the regulator is inadequate to maintain device operation, the
regulator Reset circuitry will generate a Brown-out Reset. This event is captured by the BOR flag
bit (RCON<1>). The brown-out voltage levels are listed in the specific device data sheet.
32.4.3 Voltage Regulator Tracking Mode
When the on-chip regulator is enabled, the regulator provides a constant voltage of 2.5V nominal
to the digital core logic. The regulator can provide this level from a V
DD of about 2.7V all the way
up to the devices V
DDMAX. It does not have the capability to rise the regulator output voltage to
2.5V when the V
DD drops below 2.5V. In order to prevent brown-out conditions when the
voltage drops too low for the regulator, devices with the Low-Voltage Detect (LVD) feature enter
a Tracking mode. In Tracking mode, the regulator output follows V
DD, with a typical voltage drop
of 100 mV.
Note: The ENVREG/DISVREG pins are not available on all devices. Please refer to the
specific device data sheet for more information.

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