# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Family Data Sheet

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© 2011-2012 Microchip Technology Inc. Preliminary DS39997C-page 65
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
6.1 System Reset
The PIC24FJ16MC101/102 and PIC24FJ32MC101/102/
104 family of devices have two types of Reset:
• Cold Reset
• Warm Reset
A cold Reset is the result of a POR or a BOR. On a cold
Reset, the FNOSC configuration bits in the FOSC
device configuration register selects the device clock
source.
A warm Reset is the result of all other Reset sources,
including the RESET instruction. On warm Reset, the
device will continue to operate from the current clock
source as indicated by the Current Oscillator Selection
bits (COSC<2:0>) in the Oscillator Control register
(OSCCON<14:12>).
The device is kept in a Reset state until the system
power supplies have stabilized at appropriate levels
and the oscillator clock is ready. The sequence in
which this occurs is shown in Figure 6-2.
TABLE 6-1: OSCILLATOR DELAY
Oscillator Mode
Oscillator
Startup Delay
Oscillator Startup
Timer
PLL Lock Time Total Delay
FRC, FRCDIV16, FRCDIVN T
OSCD — — T OSCD
FRCPLL T OSCD — TLOCK T OSCD + TLOCK
MS T OSCD T OST — T OSCD + T OST
HS T OSCD T OST — T OSCD + T OST
EC — — — —
MSPLL T
OSCD T OST TLOCK T OSCD + T OST + TLOCK
ECPLL — — TLOCK TLOCK
SOSC T OSCD T OST — T OSCD + T OST
LPRC T OSCD — — T OSCD
Note 1: T OSCD = Oscillator Start-up Delay (1.1 μs max for FRC, 70 μs max for LPRC). Crystal Oscillator start-up
times vary with crystal characteristics, load capacitance, etc.
2: T
OST = Oscillator Start-up Timer Delay (1024 oscillator clock period). For example, T OST = 102.4 μs for a
10 MHz crystal and T OST = 32 ms for a 32 kHz crystal.
3: T
LOCK = PLL lock time (1.5 ms nominal), if PLL is enabled.

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