# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Reset

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PIC24F Family Reference Manual
DS39712D-page 7-6 © 2011 Microchip Technology Inc.
7.2 CLOCK SOURCE SELECTION AT RESET
If clock switching is enabled (OSWEN), the system clock source at device Reset is chosen, as
displayed in Table 7-1. If clock switching is disabled, the system clock source is always selected
according to the oscillator Configuration bits. Refer to Section 6. “Oscillator” in the “PIC24F
Family Reference Manual” for further details.
Table 7-1: Oscillator Selection vs. Type of Reset (Clock Switching Enabled)
7.3 POWER-ON RESET (POR)
The POR monitors the core power supply for adequate voltage levels to ensure proper chip oper-
ation. There are two threshold voltages associated with a POR. The first voltage is the device
threshold voltage, VPOR. The device threshold voltage is the voltage at which the POR module
becomes operable. The second voltage associated with a POR event is the POR circuit threshold
voltage. Once the correct threshold voltage is detected, a power-on event occurs and the POR
module hibernates to minimize current consumption.
A power-on event generates an internal POR pulse when a V
DD rise is detected. The device
supply voltage characteristics must meet the specified starting voltage and rise rate requirements
to generate the POR pulse. In particular, V
DD must fall below VPOR before a new POR is initiated.
For more information on the V
POR and VDD rise rate specifications, refer to the “Electrical
Characteristics” section of the specific device data sheet.
The POR pulse resets the POR timer and places the device in the Reset state. The POR also
selects the device clock source identified by the oscillator Configuration bits. After the POR pulse
is generated, the POR circuit inserts a small delay, T
POR, which is nominally 5 s and ensures
that internal device bias circuits are stable.
After the expiration of T
POR, a delay, T STARTUP, is always inserted. T STARTUP is applied every
time the device resumes operation after any power-down. In the devices with an on-chip regula-
tor, the T
STARTUP parameter depends on whether the on-chip voltage regulator is enabled or
disabled. When the on-chip voltage regulator is enabled, there is a delay until the regulator can
generate a proper voltage level, referred to as T
VREG. During this time, code execution is
disabled.
If the regulator is disabled, a separate Power-up Timer (PWRT) is automatically enabled. The
PWRT adds a fixed 64 ms nominal delay at device start-up. The PWRT is used to extend the
duration of a power-up sequence when the on-chip voltage regulator is disabled and the core is
supplied from an external power supply. Hence, the T
STARTUP delay can either be TVREG (for
devices using an on-chip voltage regulator) or the Power-up Timer delay, T
PWRT (for devices not
using a regulator). The power-on event sets the BOR and POR status bits (RCON<1:0>). In
some devices, the PWRT can be disabled by using the device Configuration bit. After T
STARTUP
expires, an additional start-up time for the system clock (either T OST, TFRC or TLPRC, depending
on the source) occurs while the clock source becomes stable.
Reset Type Clock Source Selected Based on
POR
Oscillator Configuration Bits
FNOSC<2:0>
BOR
MCLR
COSC Control bits
OSCCON<14:12>
WDTR
SWR
TRAPR
IOPUWR
Note: Some device data sheets use the term, TPM (Program Memory Available Delay), in
place of T
VREG. The terms can be considered to be interchangeable.

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