# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 158 © 2005-2011 Microchip Technology Inc.
BTG
Bit Toggle in Ws
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} BTG{.B} Ws, #bit4
[Ws],
[Ws++],
[Ws--],
[++Ws],
[--Ws],
Operands: Ws ∈ [W0 ... W15]
bit4 ∈ [0 ... 7] for byte operation
bit4 ∈ [0 ... 15] for word operation
Operation: (Ws)<bit4>
→ Ws<bit4>
Status Affected: None
Encoding: 1010 0010 bbbb 0B00 0ppp ssss
Description: Bit ‘bit4’ in register Ws is toggled (complemented). For the bit4 operand,
bit numbering begins with the Least Significant bit (bit 0) and advances to
the Most Significant bit (bit 7 for byte operations, bit 15 for word
operations). Register direct or indirect addressing may be used for Ws.
The ‘b’ bits select value bit4, the bit position to test.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘s’ bits select the source/destination register.
The ‘p’ bits select the source Address mode.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: When this instruction operates in Word mode, the source
register address must be word-aligned.
3: When this instruction operates in Byte mode, ‘bit4’ must be
between 0 and 7.
4: In dsPIC33E and PIC24E devices, this instruction uses the
DSRPAG register for indirect address generation in Extended
Data Space.
Words: 1
Cycles:
1
(1)
Note 1:
In dsPIC33E and PIC24E devices, the listed cycle count does not apply to read and
read-modify-write operations on non-CPU Special Function Registers. For more
details, see
Note 3
in
Section 3.2.1 “Multi-Cycle Instructions”
.
Example 1:
BTG W2, #0x0 ; Toggle bit 0 in W2
Before
Instruction
After
Instruction
W2 F234 W2 F235
SR 0000 SR 0000

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