# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- 10-Bit ADC

- 1
- 2
…
- 50
- 51
- 52
- 53
- 54
…
- 57
- 58

PIC24F Family Reference Manual
DS39737A-page 49-52 Preliminary © 2010 Microchip Technology Inc.
49.15 OPERATION DURING SLEEP AND IDLE MODES
Sleep and Idle modes are useful for minimizing conversion noise because the digital activity of
the CPU, buses and other peripherals is minimized.
49.15.1 CPU Sleep Mode without RC A/D Clock
When the device enters Sleep mode, all clock sources to the ADC module are shut down and
stay at logic ‘0’.
If Sleep occurs in the middle of a conversion, the conversion is aborted unless the ADC is
clocked from its internal RC clock generator. The converter does not resume a partially
completed conversion on exiting from Sleep mode.
Register contents are not affected by the device entering or leaving Sleep mode.
49.15.2 CPU Sleep Mode with RC A/D Clock
The ADC module can operate during Sleep mode if the A/D clock source is set to the internal A/D
RC oscillator (ADRC = 1). This eliminates digital switching noise from the conversion. When the
conversion is completed, the DONE bit is set and the result is loaded into the ADC Result Buffer,
ADCxBUF0.
If the ADC interrupt is enabled (ADxIE = 1), the device wakes up from Sleep when the ADC
interrupt occurs. Program execution resumes at the ADC Interrupt Service Routine (ISR) if the
ADC interrupt is greater than the current CPU priority. Otherwise, execution continues from the
instruction, after the PWRSAV instruction, that placed the device in Sleep mode.
If the ADC interrupt is not enabled, the ADC module is turned off, although the ADON bit remains
set.
To minimize the effects of digital noise on the ADC module operation, the user should select a
conversion trigger source that ensures the A/D conversion will take place in Sleep mode. The
automatic conversion trigger option can be used for sampling and conversion in Sleep
(SSRC<2:0> = 111). To use the automatic conversion option, the ADON bit should be set in the
instruction before the PWRSAV instruction.
49.15.3 ADC Operation During CPU Idle Mode
For the A/D conversion, the ADSIDL bit (ADxCON1<13>) selects if the ADC module stops or
continues on Idle. If ADSIDL = 0, the ADC module continues normal operation when the device
enters Idle mode. If the ADC interrupt is enabled (ADxIE = 1), the device wakes up from Idle
mode when the ADC interrupt occurs. Program execution resumes at the ADC Interrupt Service
Routine if the ADC interrupt is greater than the current CPU priority. Otherwise, execution
continues from the instruction, after the PWRSAV instruction, that placed the device in Idle mode.
If ADSIDL = 1, the ADC module stops in Idle. If the device enters Idle mode in the middle of a
conversion, the conversion is aborted. The converter does not resume a partially completed
conversion on exiting from Idle mode.
49.16 EFFECTS OF A RESET
A device Reset forces all registers to their Reset state. This forces the ADC module to be turned
off and any conversion in progress to be aborted. All pins that are multiplexed with analog inputs
are configured as analog inputs. The corresponding TRIS bits are set.
The value in the ADCxBUF0-ADCxBUFF registers is not initialized during a Power-on Reset
(POR) and contains unknown data.
Note: For the ADC module to operate in Sleep, the ADC clock source must be set to RC
(ADRC = 1).

- 1
- 2
…
- 50
- 51
- 52
- 53
- 54
…
- 57
- 58