# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Serial Peripheral Interface

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PIC24F Family Reference Manual
DS39699B-page 23-17 Advance Information © 2007 Microchip Technology Inc.
The SPIx module follows this sequence in Enhanced Buffer Master mode:
1. Once the module is set up for Master mode of operation and enabled, data to be transmit-
ted is written to the SPIxBUF register and is loaded into the next available transmit buffer
location. The SPIxTBF bit (SPIxSTAT<1>) and SPIxIF bit are set after eight pending
transfers are loaded.
2. The current buffer location’s contents are moved to the Shift register, SPIxSR. The
SPIxTBF bit is cleared by the module if a buffer location is available for a CPU write.
3. A series of 8/16 clock pulses shift out 8/16 bits of transmit data from the SPIxSR to the
SDOx pin and simultaneously shift in the data at the SDIx pin into the SPIxSR.
4. When the transfer is complete:
• When the ongoing transmit and receive operation is complete, the contents of the
SPIxSR are moved into the next available location in the receive buffer.
• If the last unread location is written by the SPIx module, the SPIxRBF bit
(SPIxSTAT<0>) is set by the module, indicating that all buffer locations are full. SPIx
interrupts can be enabled by selecting an interrupt mode with the SISELx bits and set-
ting the SPIx Interrupt Enable bit, SPIxIE. The SPIxIF flag is not cleared automatically
by the hardware.
• Once the SPIxBUF register is read by the user code, the hardware clears the SPIxRBF
bit and the SPIxBUF increments to the next unread receive buffer location. SPIxBUF
reads beyond the last unread location will not increment the buffer location.
5. If the SPIxRBF bit is set (receive buffer is full) when the SPIx module needs to transfer
data from SPIxSR to the buffer, the module will set the SPIROV (SPIxSTAT<6>) bit,
indicating an overflow condition and set the SPIxIF bit.
6. Data to be transmitted can be written to SPIxBUF by the user software at any time as long
as the SPIxTBF (SPIxSTAT<1>) bit is clear. Up to eight pending transfers can be loaded
into the buffer allowing continuous transmission.
The timing of events in Enhanced Buffer Master mode operation is essentially the same as that
for Standard Master mode, shown in Figure 23-4.
To set up the SPIx module for the Enhanced Buffer Master mode of operation:
1. If using interrupts:
• Clear the SPIxIF bit in the respective IFSn register.
• Select an interrupt mode using the SISELx bits.
• Set the SPIxIE bit in the respective IECn register.
• Write the SPIxIP bits in the respective IPCn register.
2. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with the MSTEN bit
(SPIxCON1<5>) = 1.
3. Clear the SPIROV bit (SPIxSTAT<6>).
4. Select Enhanced Buffer mode by setting the SPIBEN bit (SPIxCON2<0>).
5. Enable SPIx operation by setting the SPIEN bit (SPIxSTAT<15>).
6. Write the data to be transmitted to the SPIxBUF register. Transmission (and reception) will
start as soon as data is written to the SPIxBUF register.
23.3.3.1.1 External Clocking in Master Mode
In Enhanced Buffer Master mode, the module can also be configured to operate with an external
data clock. SPIx clock operation is controlled by the DISSCK bit (SPIxCON1<12>). When this bit
is set, the internal data clock is disabled and data is transferred when external clock pulses are
presented on the SCKx pin. All other aspects of Standard Master mode operation are the same
as before.
Note: The DISSCK bit is available only in SPI Master modes.

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