# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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dsPIC33/PIC24 Family Reference Manual
DS70000195F-page 36  2007-2014 Microchip Technology Inc.
6.6 Bus Collision During a Repeated Start Condition
When the two masters do not collide throughout an address byte, a bus collision can occur when
one master attempts to assert a Repeated Start while another transmits data. In this case, the
master generating the Repeated Start loses arbitration and generates a bus collision interrupt.
6.7 Bus Collision During Message Bit Transmission
The most typical case of data collision occurs while the master is attempting to transmit the
device address byte, a data byte or an Acknowledge bit.
If the user software is properly checking the bus state, it is unlikely that a bus collision will occur
on a Start condition. However, because another master can, at the same time, check the bus and
initiate its own Start condition, it is likely that SDAx arbitration will occur and synchronize the Start
of two masters. In this condition, both masters begin and continue to transmit their messages
until one master loses arbitration on a message bit. The SCLx clock synchronization keeps the
two masters synchronized until one loses arbitration. Figure 6-2 illustrates an example of the
message bit arbitration.
Figure 6-2: Bus Collision During Message Bit Transmission
6.8 Bus Collision During a Stop Condition
If the master software loses track of the state of the I
2
C bus, many existing conditions can
cause a bus collision during a Stop condition. In this case, the master generating the Stop
condition will lose arbitration and generate a bus collision interrupt.
Note: The bus collision interrupt is not available on all devices. Refer to the specific device
data sheet for availability.
SCLx (Master)
SDAx (Master)
TBF
TBRG
1 2 3
Master transmits bit value of ‘1’ in next SCLx clock.
1
TBRG
Module releases SDAx.
Another master on bus transmits bit value of ‘0’
2
in next SCLx clock. Another master pulls SDAx low.
BRG times out. Module attempts to verify SDAx high.
3
I
2
C™ Bus State
BCL
(D)
SCLx (Bus)
SDAx (Bus)
Bus collision detected.
Module releases SDAx and SCLx. Module sets BCL status bit
and clears the TBF status bit. Master generates the interrupt.
(D)(Q)
(Q) (Q)
MI2CxIF Interrupt

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