# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- UART

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 2009-2013 Microchip Technology Inc. DS70000582E-page 5
UART
Register 2-1: UxMODE: UARTx Mode Register
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
UARTEN
(3)
 USIDL IREN
(1)
RTSMD ALTIO
(2)
UEN1
(2)
UEN0
(2)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WAKE
(4)
LPBACK ABAUD
(5)
URXINV BRGH PDSEL1 PDSEL0 STSEL
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
bit 15 UARTEN: UARTx Enable bit
(3)
1 = UARTx is enabled; UARTx pins are controlled by UARTx as defined by the UEN<1:0> and
UTXEN control bits
0 = UARTx is disabled; UARTx pins are controlled by the corresponding PORTx, LATx and TRISx bits
bit 14 Unimplemented: Read as 0
bit 13 USIDL: UARTx Stop in Idle Mode bit
1 = Discontinues operation when the device enters Idle mode
0 = Continues operation in Idle mode
bit 12 IREN: IrDA
®
Encoder and Decoder Enable bit
(1)
1 = IrDA encoder and decoder are enabled
0 = IrDA encoder and decoder are disabled
bit 11 RTSMD: Mode Selection for UxRTS
Pin bit
1 = UxRTS is in Simplex mode
0 = UxRTS
is in Flow Control mode
bit 10 ALTIO: UARTx Alternate I/O Selection bit
(2)
1 = UARTx communicates using UxATX and UxARX I/O pins
0 = UARTx communicates using UxTX and UxRX I/O pins
bit 9-8 UEN<1:0>: UARTx Enable bits
(2)
11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin is controlled by port latches
10 = UxTX, UxRX, UxCTS
and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS
pins are enabled and used; UxCTS pin is controlled by port latches
00 = UxTX and UxRX pins are enabled and used; UxCTS
, UxRTS and BCLKx pins are controlled by
port latches
bit 7 WAKE: Enable Wake-up on Start bit Detect During Sleep Mode bit
(4)
1 = Wake-up is enabled
0 = Wake-up is disabled
bit 6 LPBACK: UARTx Loopback Mode Select bit
1 = Enables Loopback mode
0 = Loopback mode is disabled
Note 1: This feature is only available for Standard Speed mode (BRGH = 0). Refer to the “Universal Asynchronous
Receiver Transmitter (UART)” chapter of the specific device data sheet for availability.
2: These features may not be available on all devices. Refer to the “Universal Asynchronous Receiver
Transmitter (UART)” chapter of the specific device data sheet for availability.
3: Enable this bit before enabling the UTXEN bit (UxSTA<10>).
4: The UARTx module does not recognize the first character received on a wake.
5: The use of this feature may consume the corresponding Input Capture x (ICx) peripheral. See Section 9.2
“Auto-Baud Support” for more information.

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