# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 -- Serial Peripheral Interface

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 2014 Microchip Technology Inc. DS70005185A-page 9
Serial Peripheral Interface (SPI) Module
bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)
(3)
111 = Secondary prescale 1:1
110 = Secondary prescale 2:1
•
•
•
000 = Secondary prescale 8:1
bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)
(3)
11 = Primary prescale 1:1
10 = Primary prescale 4:1
01 = Primary prescale 16:1
00 = Primary prescale 64:1
Register 2-2: SPI
XCON1: SPIx Control Register 1 (Continued)
Note 1: The CKE bit is not used in Framed SPI modes. Program this bit to ‘0’ for Framed SPI modes (FRMEN = 1).
2: The SMP bit must be set only after setting the MSTEN bit. The SMP bit remains clear if MSTEN = 0.
3: Do not set the primary and secondary prescalers to the value of 1:1 at the same time.
4: This bit must be cleared when FRMEN = 1.
5: If DISSCK = 1, the SCKx pin becomes a regular I/O and can be controlled using the TRISx and LATx reg-
isters, but internally, the SCKx clock may not be disconnected from the receiving part of the SPIx module
and the data will still be captured from the SDIx pin. To avoid an overflow error, the application may need
to read the SPIx buffer after the transmission.

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