# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 66 © 2005-2011 Microchip Technology Inc.
4.5 WORD MOVE OPERATIONS
Even though the data space is byte addressable, all move operations made in Word mode must
be word-aligned. This means that for all source and destination operands, the Least Significant
address bit must be ‘0’. If a word move is made to or from an odd address, an address error
exception is generated. Likewise, all double words must be word-aligned.
Figure 4-3 shows how
bytes and words may be aligned in data memory. Example 4-10 contains several legal word
move operations.
When an exception is generated due to a misaligned access, the exception is taken after the
instruction executes. If the illegal access occurs from a data read, the operation will be allowed
to complete, but the Least Significant bit of the source address will be cleared to force word
alignment. If the illegal access occurs during a data write, the write will be inhibited.
Example 4-11
contains several illegal word move operations.
Figure 4-3: Data Alignment in Memory
0x1001 b0 0x1000
0x1003
b1 0x1002
0x1005 b3 b2 0x1004
0x1007
b5 b4 0x1006
0x1009
b7 b6 0x1008
0x100B b8 0x100A
Legend:
b0 – byte stored at 0x1000
b1 – byte stored at 0x1003
b3:b2 – word stored at 0x1005:1004 (b2 is LSB)
b7:b4 – double word stored at 0x1009:0x1006 (b4 is LSB)
b8 – byte stored at 0x100A
Note: Instructions that operate in Word mode are not required to use an instruction
extension. However, they may be specified with an optional “.w” or “.W” extension,
if desired. For example, the following instructions are valid forms of a word clear
operation:
• CLR W0
• CLR.w W0
• CLR.W W0

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