# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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dsPIC33/PIC24 Family Reference Manual
DS70000195F-page 12  2007-2014 Microchip Technology Inc.
bit 7 GCEN: General Call Enable bit (I
2
C Slave mode only)
1 = Enables the interrupt when a general call address is received in I2CxRSR; the module is enabled for
reception
0 = General call address is disabled
bit 6 STREN: SCLx Clock Stretch Enable bit
In I
2
C Slave mode only; used in conjunction with the SCLREL bit.
1 = Enables clock stretching
0 = Disables clock stretching
bit 5 ACKDT: Acknowledge Data bit
In I
2
C Master mode during Master Receive mode. The value that will be transmitted when the user
initiates an Acknowledge sequence at the end of a receive.
In I
2
C Slave mode when AHEN = 1 or DHEN = 1. The value that the slave will transmit when it initiates
an Acknowledge sequence at the end of an address or data reception.
1 = NACK is sent
0 = ACK is sent
bit 4 ACKEN: Acknowledge Sequence Enable bit
In I
2
C Master mode only; applicable during Master Receive mode.
1 = Initiates the Acknowledge sequence on the SDAx and SCLx pins, and transmits the ACKDT data bit
0 = Acknowledge sequence is in Idle mode
bit 3 RCEN: Receive Enable bit (I
2
C Master mode only)
1 = Enables Receive mode for I
2
C; automatically cleared by hardware at the end of an 8-bit receive
data byte
0 = Receive sequence is not in progress
bit 2 PEN: Stop Condition Enable bit (I
2
C Master mode only)
1 = Initiates the Stop condition on the SDAx and SCLx pins
0 = Stop condition is in Idle mode
bit 1 RSEN: Restart Condition Enable bit (I
2
C Master mode only)
1 = Initiates the Restart condition on the SDAx and SCLx pins
0 = Restart condition is in Idle mode
bit 0 SEN: Start Condition Enable bit (I
2
C Master mode only)
1 = Initiates the Start condition on the SDAx and SCLx pins
0 = Start condition is in Idle mode
Register 3-2: I2CxCONL: I2Cx Control Register Low (Continued)
Note 1: Automatically cleared to ‘0’ at the beginning of the slave transmission; automatically cleared to ‘0’ at the
end of the slave reception.
2: Automatically cleared to ‘0’ at the beginning of the slave transmission.

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