# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# MPLAB XC16 C-Compiler

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MPLAB
®
XC16 C COMPILER
USERS GUIDE
 2012-2013 Microchip Technology Inc. DS50002071C-page 191
Chapter 14. Interrupts
14.1 INTRODUCTION
Interrupt processing is an important aspect of most microcontroller applications.
Interrupts may be used to synchronize software operations with events that occur in
real time. When interrupts occur, the normal flow of software execution is suspended
and special functions are invoked to process the event. At the completion of interrupt
processing, previous context information is restored and normal execution resumes.
This chapter presents an overview of interrupt processing. The following items are
discussed:
 Interrupt Operation  An overview of how interrupts operate.
 Writing an Interrupt Service Routine  You can designate one or more C
functions as Interrupt Service Routines (ISRs) to be invoked by the occurrence of
an interrupt. For best performance in general, place lengthy calculations or opera-
tions that require library calls in the main application. This strategy optimizes
performance and minimizes the possibility of losing information when interrupt
events occur rapidly.
 Specifying the Interrupt Vector  The 16-bit devices use interrupt vectors to
transfer application control when an interrupt occurs. An interrupt vector is a
dedicated location in program memory that specifies the address of an ISR.
Applications must contain valid function addresses in these locations to use
interrupts.
 Interrupt Service Routine Context Saving  To handle returning from an
interrupt to code in the same conditional state as before the interrupt, context
information from specific registers must be saved.
 Nesting Interrupts  The time between when an interrupt is called and when the
first ISR instruction is executed is the latency of the interrupt.
 Enabling/Disabling Interrupts  How interrupt priorities are determined.
Enabling and disabling interrupt sources occurs at two levels: globally and individ-
ually.
 ISR Considerations Sharing memory with mainline code, PSV usage with ISRs,
and calling functions within ISRs.

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