# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 12 © 2005-2011 Microchip Technology Inc.
2.1.2.5 DSP CONTEXT SWITCH SUPPORT (dsPIC33E ONLY)
In dsPIC33E devices, the DSP overflow and saturation status bits are writable. This allows the
state of the DSP Engine to be efficiently saved and restored while switching between DSP tasks.
See 2.16.4 “DSP ALU Status Bits (dsPIC30F, dsPIC33F and dsPIC33E Devices)” for more
details on DSP status bits.
2.1.2.6 EXTENDED CALL AND GOTO INSTRUCTIONS
The new CALL.L Wn and GOTO.L Wn instructions extend the capabilities of the CALL Wn and
GOTO Wn by enabling 32-bit addresses for computed branch/call destinations. In these
enhanced instructions, the destination address is provided by a pair of working registers rather
than a single 16-bit register. See the CALL.L and GOTO.L instruction descriptions in
5.4 “Instruction Descriptions” for more details.
2.1.2.7 COMPARE-BRANCH INSTRUCTIONS
dsPIC33E/PIC24E devices feature conditional Compare-Branch (CPBxx) instructions. These
instructions extend the capabilities of the Compare-Skip (CPSxx) instructions by allowing
branches rather than only skipping over a single instruction. See the CPBEQ, CPBNE, CPBGT
and CPBLT instruction descriptions in
5.4 “Instruction Descriptions” for more details on
compare-branch instructions.
2.1.3 dsPIC30F, dsPIC33F, and dsPIC33E Features
In addition to the information provided in Section 2.1.1 “Features Specific to 16-bit MCU and
DSC Core”, this section describes the DSP enhancements that are available in the dsPIC30F,
dsPIC33F, and dsPIC33E families of devices.
2.1.3.1 PROGRAMMING LOOP CONSTRUCTS
Overhead free program loop constructs are supported using the DO instruction, which is
interruptible.
2.1.3.2 DSP INSTRUCTION CLASS
The DSP class of instructions.are seamlessly integrated into the architecture and execute from
a single execution unit.
2.1.3.3 DATA SPACE ADDRESSING
The data space is split into two blocks, referred to as X and Y data memory. Each memory block
has its own independent Address Generation Unit (AGU). The MCU class of instructions operate
solely through the X memory AGU, which accesses the entire memory map as one linear data
space. The DSP dual source class of instructions operates through the X and Y AGUs, which
splits the data address space into two parts. The X and Y data space boundary is arbitrary and
device-specific.
2.1.3.4 MODULO AND BIT-REVERSED ADDRESSING
Overhead-free circular buffers (modulo addressing) are supported in both X and Y address
spaces. The modulo addressing removes the software boundary checking overhead for DSP
algorithms. Furthermore, the X AGU circular addressing can be used with any of the MCU class
of instructions. The X AGU also supports bit-reverse addressing, to greatly simplify input or
output data reordering for radix-2 FFT algorithms.
2.1.3.5 DSP ENGINE
The DSP engine features a high-speed, 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bit
saturating accumulators and a 40-bit bidirectional barrel shifter. The barrel shifter is capable of
shifting a 40-bit value, up to 16 bits right, or up to 16 bits left, in a single cycle. The DSP
instructions operate seamlessly with all other instructions and have been designed for optimal
real-time performance. The MAC instruction and other associated instructions can concurrently
fetch two data operands from memory while multiplying two working registers. This requires that

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