# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- UART

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dsPIC33/PIC24 Family Reference Manual
DS70000582E-page 28  2009-2013 Microchip Technology Inc.
8.5 Address Match Detect
The UART has a built-in feature that can perform address match detection to off-load this task from
the processors. The ADM_ADD<7:0> (UxADMD<7:0>) address and ADM_MASK<7:0>
(UxADMD<15:8>) address mask bits are used to hold the desired address and mask bits, respec-
tively. If ADDEN = 1 and the 9th bit received is a 1, the data in the Receive Shift register is
compared to the ADM_ADDx bits and masked with the ADM_MASKx bits. If a match is found, the
data is transferred from the Receive Shift register to the UxRXBUF according to Table 8-1.
If an address match is found, software must clear ADDEN = 0 to receive the remainder of the
message; interrupts on the body of the message will occur as specified by URXISEL<1:0>
(UxSTA<7:6>). After the body of the message is received, software must set ADDEN = 1 to
enable Address Detect mode once again.
8.5.1 USING ADDRESS MATCH DETECT
The setup procedure for 9-bit reception is similar to the procedure for 8-Bit Receive modes,
except that the PDSEL<1:0> bits (UxMODE<2:1>) should be set to 11 (see Section 7.4 “Setup
for UART Reception”).
1. Write the desired match address to ADM_ADDR<7:0>.
2. Write the desired address mask to ADM_MASK<7:0>.
3. Set PDSEL<1:0> = 11 to choose 9-bit mode.
4. Set ADDEN = 1 to enable automatic address detection.
5. When an interrupt is received, the matching address will be stored in the UxRXBUF. If a
mask is being used for decision logic, user software can read it from UxRXBUF. If the
address is not needed, it should be cleared from the buffer with a dummy read.
6. Clear ADDEN to allow the reception of the following data. Interrupts on the body of the
message will occur as specified by URXISEL<1:0>.
7. When reception of the body of message is completed (as determined in the application
software), set the ADDEN bit to 1 to detect the next message address.
Note: Not all devices support address match detect. Refer to the specific device data
sheet for availability.
Table 8-1: Address Match Detection
Condition Action
(UxRSR<7:0> and ADM_MASK<7:0>) = (ADM_ADDR<7:0>
and ADM_MASK<7:0>)
(1)
UxBUF = UxRSR<7:0>
(UxRSR<7:0> and ADM_MASK<7:0>) ≠ (ADM_ADDR<7:0>
and ADM_MASK<7:0>)
(1)
None, UxRSR will be
overwritten with next
incoming byte
Note 1: ADM_MASKx bits set to 0 are regarded as dont care for that address bit position.
Note: The URXISEL<1:0> control bits do not have any impact on the interrupt generation
in this mode. If the 9th bit is a 1, an interrupt is generated, regardless of the state
of the URXISEL<1:0> bits.

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