# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- CPU

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PIC24F Family Reference Manual
DS39703A-page 2-18 Advance Information © 2006 Microchip Technology Inc.
2.9 INSTRUCTION FLOW TYPES
Most instructions in the PIC24F architecture occupy a single word of program memory and
execute in a single cycle. An instruction prefetch mechanism facilitates single-cycle (1 T
CY)
execution. However, some instructions take 2 or 3 instruction cycles to execute. Consequently,
there are six different types of instruction flow in the PIC24F architecture. These are described
below:
1. 1 Instruction Word, 1 Instruction Cycle:
These instructions will take one instruction cycle to execute as shown in Example 2-6.
Example 2-6: Instruction Flow – 1-Word, 1-Cycle
2. 1 Instruction Word, 2 Instruction Cycles:
These instructions include the relative branches, relative call, skips and returns. When an
instruction changes the PC (other than to increment it), the pipelined fetch is discarded. This
makes the instruction take two effective cycles to execute as shown in Example 2-7.
Example 2-7: Instruction Flow – 1-Word, 2-Cycle
3. 1 Instruction Word, 2 Instruction Cycles (Double Operation):
The only instructions of this type are the LDDW and STDW (load and store double word). As
the data access has to be sequential, two cycles are required to complete these instructions
as shown in Example 2-8.
Example 2-8: Instruction Flow – 1-Word, 2-Cycle
T CY0 T CY1 T CY2 T CY3 T CY4 T CY5
1. MOV #350, W0
Fetch 1 Execute 1
2. INC W0, W2
Fetch 2 Execute 2
3. INC [W0++], W2
Fetch 3 Execute 3
T CY0 T CY1 T CY2 T CY3 T CY4 T CY5 T CY6
1. MOV #55, W0
Fetch 1 Execute 1
2. BTSC.b PORTA, #3
Fetch 2 Execute 2
Skip Taken
3. ADD.b, PORTB
Fetch 3 Forced NOP
4. BRA SUB_1
Fetch 4 Execute 4
5. ADD.b W0, [W1], [W2]
Fetch 5 Forced NOP
| | |
6. Instruction @ address SUB_1
Fetch
SUB_1
Execute
SUB_1
T CY0 T CY1 T CY2 T CY3 T CY4 T CY5
1. MOV.w #1234, W2
Fetch 1 Execute 1
2. MOV.D [W2++], W4
Fetch 2 Execute 2
R/W Cycle 1
Execute 2
R/W Cycle 2
3. MOV.w 0x0AA, W0
Fetch 3 No Fetch Execute 3
4. MOV.b, PORTA
Fetch 4 Execute 4

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