# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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 2007-2014 Microchip Technology Inc. DS70000195F-page 71
Inter-Integrated Circuit™ (I
2
C™)
Revision F (February 2014)
This revision includes the following updates:
• Sections:
- Updated Section 1.0 “Introduction”
- Updated Section 3.0 “Control and Status Registers”
- Updated Section 4.0 “Enabling I
2
C Operation”, Section 5.0 “Communicating as a
Master in a Single Master Environment”
- Included Section 5.2.2 “STRICT Support in Master Mode”
- Updated Section 6.3 “Bus Arbitration and Bus Collision”, Section 6.4 “Detecting
Bus Collisions and Re-Sending Messages”
- Included Section 7.2.1 “Interrupt on Start/Repeated Start and Stop Conditions
(Slave Mode)”
- Updated Section 7.3.2 “7-Bit Address and Slave Write”
- Included Section 7.3.3 “7-Bit Address and Slave Write with the AHEN and DHEN
Bits”
- Updated Section 7.3.4 “7-Bit Address and Slave Read”
- Included Section 7.3.6 “Slave Mode Bus Collision”
- Updated note in Section 7.3.7 “General Call Operation”
- Included Section 7.3.9 “STRICT Support”
- Note included in Section 5.4 “Acknowledge Generation”
- Included Section 7.4.2 “Receive Buffer Overwrite (I
2
C Slave Mode Only)”
- Updated Section 14.0 “Design Tips”
• Figures
- Updated Figure 1-1, Figure 2-1, Figure 7-2, Figure 7-5, Figure 7-7, Figure 7-9,
Figure 7-11, Figure 7-12, Figure 7-13 and Figure 7-14
- Included new Figure 7-17
• Tables
- Update Table 5-1
- Updated note in Table 7-2
- Updated Table 7-3
• Registers
- Added Register 3-2 and Register 3-3
- Updated Register 3-4
- Updated register map Table 13-1
• Equation
- Updated Equation 4-1
• Additional minor corrections, such as language and formatting updates, were incorporated
throughout the document.

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