# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 -- Serial Peripheral Interface

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 2014 Microchip Technology Inc. DS70005185A-page 17
Serial Peripheral Interface (SPI) Module
3.3.2 SLAVE MODE
In Slave mode, the data is transmitted and received as the external clock pulses appear on the
SCKx pin. The CKP bit (SPIxCON<6>) and the CKE bit (SPIxCON<8>) determine the edge of
the clock pulse when the data transmission occurs. Data to be transmitted and data that is
received are written into or read from the SPIxBUF register. The remaining module operation is
identical to that of Master mode.
3.3.2.1 Slave Mode Setup Procedure
The following procedure is used to set up the SPIx module for the Slave mode of operation:
1. Clear the SPIxBUF register.
2. If using interrupts, configure the interrupt controller:
a) Clear the SPIx Interrupt Flag Status bit (SPIxIF) in the respective IFSx register.
b) Set the SPIx Interrupt Enable Control bit (SPIxIE) in the respective IECx register.
c) Write the SPIx Interrupt Priority Control (SPIxIP) bits in the respective IPCx register
to set the interrupt priority.
3. Configure the SPIxCON1 register:
a) Clear the Master Mode Enable (MSTEN) bit (SPIxCON1<5> = 0).
b) Clear the Data Input Sample Phase (SMP) bit (SPIxCON1<9> = 0).
c) If the Clock Edge Select (CKE) bit is set, set the Slave Select Enable (SSEN) bit to
enable the SSx
pin (SPIxCON1<7> = 1).
4. Configure the SPIxSTAT register:
a) Clear the Receive Overflow Flag (SPIROV) bit (SPIxSTAT<6> = 0).
b) Set the SPIx Enable (SPIEN) bit (SPIxSTAT<15> = 1) to enable SPIx operation.
Example 3-2 provides the code sequence to show the SPIx register configuration for Slave mode
(the SPI1 module is used in the example).
Example 3-2: SPI1 Register Configuration – Slave Mode
Note 1: In Slave mode, the SPIx clock frequency on the SCKx pin must be lower than the
device system frequency (FSCK < FCY).
2: In Slave mode, if no data is written to the SPIxBUF register when the SPIx master
initiates a read operation, SPI mode will transmit the last data that was written into
the SPIxBUF register.
/* The following code sequence shows SPI register configuration for Slave mode */
SPI1BUF = 0;
IFS0bits.SPI1IF = 0; // Clear the Interrupt flag
IEC0bits.SPI1IE = 0; // Disable the interrupt
// SPI1CON1 Register Settings
SPI1CON1bits.DISSCK = 0; // Internal Serial Clock is enabled
SPI1CON1bits.DISSDO = 0; // SDOx pin is controlled by the module
SPI1CON1bits.MODE16 = 1; // Communication is word-wide (16 bits)
SPI1CON1bits.SMP = 0; // Input data is sampled at the middle of data
// output time.
SPI1CON1bits.CKE = 0; // Serial output data changes on transition
// from Idle clock state to active clock state
SPI1CON1bits.CKP = 0; // Idle state for clock is a low level; active
// state is a high level
SPI1CON1bits.MSTEN = 0; // Master mode disabled
SPI1STATbits.SPIROV=0; // No Receive Overflow has occurred
SPI1STATbits.SPIEN = 1; // Enable SPI module
// Interrupt Controller Settings
IFS0bits.SPI1IF = 0; // Clear the Interrupt flag
IEC0bits.SPI1IE = 1; // Enable the interrupt

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