# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- 10-Bit ADC

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© 2010 Microchip Technology Inc. Preliminary DS39737A-page 49-25
Section 49. 10-Bit ADC with 4 Simultaneous Conversions
10-Bit ADC with
4 Simultaneous
Conversions
49
49.5 ADC INTERRUPT GENERATION
As conversions are completed, the ADC module writes the results of the conversions into the
Analog-to-Digital result buffer. The ADC result buffer is an array of sixteen words, accessed
through the SFR space. The user application may attempt to read each Analog-to-Digital
conversion result as it is generated. However, this might consume too much CPU time.
Generally, to simplify the code, the module fills the buffer with results and generates an interrupt
when the buffer is filled. The ADC module supports 16 result buffers. Therefore, the maximum
number of conversions per interrupt must not exceed 16.
The number of conversions per ADC interrupt depends on the following parameters, which can
vary from one to 16 conversions per interrupt.
• Number of S&H Channels Selected
• Sequential or Simultaneous Sampling
• Samples Convert Sequences Per Interrupt bit (SMPI<3:0>) Settings
Table 49-7 lists the number of conversions per ADC interrupt for different configuration modes.
Table 49-7: Samples Per Interrupt in Alternate Sampling Mode
The DONE bit (ADxCON1<0>) is set when an ADC interrupt is generated to indicate completion
of a required sample/conversion sequence. This bit is automatically cleared by the hardware at
the beginning of the next sample/conversion sequence.
Interrupt generation is based on the SMPI<3:0> and CHPS bits, so the DONE bit is not set after
every conversion, but is set when the ADC Interrupt Flag (ADxIF) is set.
49.5.1 Buffer Fill Mode
When the Buffer Fill Mode bit (BUFM) in the ADC Control Register 2 (ADxCON2<1>) is ‘1’, the
16-word results buffer is split into two 8-word groups: a lower group (ADC1BUF0 through
ADC1BUF7) and an upper group (ADC1BUF8 through ADC1BUFF). The 8-word buffers
alternately receive the conversion results after each ADC interrupt event. When the BUFM bit is
set, each buffer size is equal to eight. Therefore, the maximum number of conversions per
interrupt must not exceed eight.
When the BUFM bit is ‘0’, the complete 16-word buffer is used for all conversion sequences. The
decision to use the split buffer feature depends on the time available to move the buffer contents,
after the interrupt, as determined by the application.
If the application can quickly unload a full buffer within the time taken to sample and convert one
channel, the BUFM bit can be ‘0’, and up to 16 conversions may be done per interrupt. The
application has one sample/convert time before the first buffer location is overwritten. If the
processor cannot unload the buffer within the sample and conversion time, the BUFM bit should
be ‘1’. For example, if an ADC interrupt is generated every eight conversions, the processor has
the entire time between interrupts to move the eight conversions out of the buffer.
49.5.2 Buffer Fill Status
When the conversion result buffer is split using the BUFM control bit, the BUFS status bit
(ADxCON2<7>) indicates half of the buffer that the ADC module is currently writing. If BUFS = 0,
the ADC module is filling the lower group and the user application should read conversion values
from the upper group. If BUFS = 1, the situation is reversed and the user application should read
conversion values from the lower group.
CHPS<1:0> SIMSAM SMPI<3:0>
Conversions/
Interrupt
Description
00 x N-1 N 1-Channel mode
01 0 N-1 N 2-Channel Sequential Sampling mode
1x 0 N-1 N 4-Channel Sequential Sampling mode
01 1 N-1 2 • N 2-Channel Simultaneous Sampling mode
1x 1 N-1 4 • N 4-Channel Simultaneous Sampling mode
Note 1: In 2-Channel Simultaneous Sampling mode, SMPI<3:0> bit settings must be less
than eight.
2: In 4-Channel Simultaneous Sampling mode, SMPI<3:0> bit settings must be less
than four.

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