# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004

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PIC24FJ64GA004 FAMILY
DS39881E-page 56  2010-2013 Microchip Technology Inc.
6.1 Clock Source Selection at Reset
If clock switching is enabled, the system clock source at
device Reset is chosen, as shown in Table 6-2. If clock
switching is disabled, the system clock source is always
selected according to the Oscillator Configuration bits.
Refer to Section 8.0 “Oscillator Configuration” for
further details.
TABLE 6-2: OSCILLATOR SELECTION vs.
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
6.2 Device Reset Times
The Reset times for various types of device Reset are
summarized in Table 6-3. Note that the system Master
Reset Signal, SYSRST
, is released after the POR and
PWRT delay times expire.
The time that the device actually begins to execute
code will also depend on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the PLL lock time. The OST and PLL lock times occur
in parallel with the applicable SYSRST
delay times.
The FSCM delay determines the time at which the
FSCM begins to monitor the system clock source after
the SYSRST
signal is released.
TABLE 6-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
Reset Type Clock Source Determinant
POR FNOSC<2:0> Configuration bits
(CW2<10:8>)
BOR
MCLR
COSC<2:0> Control bits
(OSCCON<14:12>)
WDTO
SWR
Reset Type Clock Source SYSRST Delay
System Clock
Delay
Notes
POR
(6)
EC TPOR
+ TPWRT + TRST  1, 2, 7
FRC, FRCDIV T
POR
+ TPWRT + TRST TFRC 1, 2, 3, 7
LPRC TPOR
+ TPWRT + TRST TLPRC 1, 2, 3, 7
ECPLL TPOR
+ TPWRT + TRST TLOCK 1, 2, 4, 7
FRCPLL T
POR
+ TPWRT + TRST TFRC + TLOCK 1, 2, 3, 4, 7
XT, HS, SOSC TPOR
+ TPWRT + TRST T OST 1, 2, 5, 7
XTPLL, HSPLL TPOR
+ TPWRT + TRST T OST + TLOCK 1, 2, 4, 5, 7
BOR EC T
PWRT + T RST  2, 7
FRC, FRCDIV TPWRT + T RST TFRC 2, 3, 7
LPRC TPWRT + T RST TLPRC 2, 3, 7
ECPLL T
PWRT + T RST TLOCK 2, 4, 7
FRCPLL T
PWRT + T RST TFRC + TLOCK 2, 3, 4, 7
XT, HS, SOSC TPWRT + T RST T OST 2, 5, 7
XTPLL, HSPLL T
PWRT + T RST TFRC + TLOCK 2, 3, 4, 7
All Others Any Clock T
RST  7
Note 1: T
POR = Power-on Reset delay.
2: T
PWRT = 64 ms nominal if regulator is disabled (ENVREG tied to VSS).
3: T
FRC and TLPRC = RC Oscillator Start-up Times.
4: T
LOCK = PLL Lock Time.
5: T
OST = Oscillator Start-up Timer (OST). A 10-bit counter waits 1024 oscillator periods before releasing the
oscillator clock to the system.
6: If Two-Speed Start-up is enabled, regardless of the primary oscillator selected, the device starts with FRC,
and in such cases, FRC start-up time is valid.
7: T
RST
= Internal State Reset Timer

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