# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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dsPIC33/PIC24 Family Reference Manual
DS70000195F-page 38  2007-2014 Microchip Technology Inc.
7.3 Detecting the Address
Once the module has been enabled, the slave waits for a Start condition to occur. After a Start,
depending on the A10M bit (I2CxCON<10> or I2CxCONL<10>), the slave attempts to detect a
7-bit or 10-bit address. The slave compares one received byte for a 7-bit address or two received
bytes for a 10-bit address. A 7-bit address also contains an R/W
status bit that specifies the direc-
tion of the data transfer after the address. If R/W
= 0, a write is specified and the slave receives
data from the master. If R/W
= 1, a read is specified and the slave sends data to the master. The
10-bit address contains an R/W
status bit; however, by definition, it is always R/W = 0 because
the slave must receive the second byte of the 10-bit address.
7.3.1 SLAVE ADDRESS MASKING
The I2CxMSK register masks the address bit positions, designating them as “don’t care” bits for
both 10-Bit and 7-Bit Addressing modes. When a bit in the I2CxMSK register is set (= 1), the
slave responds when the bit in the corresponding location of the address is a ‘0’ or ‘1’. For
example, in 7-Bit Slave mode with I2CxMSK = 0100000, the slave module Acknowledges
addresses, ‘0000000’ and ’0100000’, as valid.
To enable address masking, the IPMI must be disabled by clearing the IPMIEN bit
(I2CxCON<11>).
7.3.2 7-BIT ADDRESS AND SLAVE WRITE
After the Start condition, the module shifts 8 bits into the I2CxRSR register, as illustrated in
Figure 7-2. The value of the I2CxRSR register is evaluated against that of the I2CxADD and
I2CxMSK registers on the falling edge of the eighth clock (SCLx). If the address is valid (that is,
an exact match between unmasked bit positions), the following events occur:
• An ACK
is generated if the AHEN bit is clear
• The D/A
and R/W status bits are cleared
• The module generates the SI2CxIF interrupt on the falling edge of the ninth SCLx clock
• The module waits for the master to send data
Figure 7-2: Slave Write 7-Bit Address Detection Timing Diagram
Note: The AHEN bit may not be available on all devices. Refer to the specific device data
sheet for availability. If this bit is not present, then the device will generate an (ACK
)
on an address match.
SCLx (Master)
SDAx (Master)
SDAx (Slave)
SI2CxIF Interrupt
4 5
1
3
Detecting Start bit enables
1
I
2
C™ Bus State
(D) (D) (A)(D)
A5A6A7 A4 A3 A2 A1
D/A
ADD10
SCLREL
R/W
address detection. If SCIE is set, then
R/W
= 0 indicates that slave
3
receives data bytes.
Valid address of first byte clears
4
D/A
status bit. Slave generates an
R/W
status bit cleared. Slave
5
generates interrupt.
6
Bus waiting. Slave ready to
6
receive data.
R/W = 0
(S) (Q)
2
2
User software clears the interrupt
flag.
(1)
Note 1: The SCIE bit may not be available on all devices. Refer to the specific device data sheet for availability.
the slave interrupt is asserted.
(1)
ACK.

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