# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Family Data Sheet

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PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
DS39997C-page 338 Preliminary © 2011-2012 Microchip Technology Inc.
Section 7.0 “Interrupt
Controller”
Updated the Interrupt Vectors (see Table 7-1).
The following registers were updated or added:
• Register 7-5: IFS0: Interrupt Flag Status Register 0
• Register 7-11: IEC1: Interrupt Enable Control Register 1
• Register 7-21: IPC6: Interrupt Priority Control Register 6
Section 9.0 “Power-
Saving Features”
Updated Register 9-1: PMD1: Peripheral Module Disable Control Register 1.
Section 10.0 “I/O Ports” Updated TABLE 10-1: Selectable Input Sources (Maps Input to Function)
(1)
.
Updated TABLE 10-2: Output Selection for Remappable Pin (RPn)
The following registers were updated or added:
• Register 10-4: RPINR4: Peripheral Pin Select Input Register 4
• Register 10-6: RPINR8: Peripheral Pin Select Input Register 8
• Register 10-19: RPOR8: Peripheral Pin Select Output Register 8
• Register 10-20: RPOR9: Peripheral Pin Select Output Register 9
• Register 10-21: RPOR10: Peripheral Pin Select Output Register 10
• Register 10-22: RPOR11: Peripheral Pin Select Output Register 11
• Register 10-23: RPOR12: Peripheral Pin Select Output Register 12
Section 12.0 “Timer2/3
Feature”
The features and operation information was extensively updated in support of Timer4/5
(see Section 12.1 “32-bit Operation” and Section 12.2 “16-bit Operation”).
The block diagrams were updated in support of the new timers (see Figure 12-1,
Figure 12-2, and Figure 12-3).
The following registers were added:
• Register 12-3: T4CON Control Register
• Register 12-4: T5CON Control Register
Section 15.0 “Motor
Control PWM Module”
Updated TABLE 15-1: Internal Pull-down resistors on PWM Fault pins.
Note 2 was added to Register 15-5: PWMXCON1: PWM Control Register 1
(1)
.
Section 19.0 “10-bit
Analog-to-Digital
Converter (ADC)”
The number of available input pins and channels were updated from six to 14.
Updated FIGURE 19-1: ADC1 Block Diagram for PIC24FJXXMC101 Devices.
Updated FIGURE 19-2: ADC1 Block Diagram for PIC24FJXXMC102 Devices.
Added FIGURE 19-3: ADC1 Block Diagram for PIC24FJXXMC104 Devices.
The following registers were updated:
• Register 19-4: AD1CHS123: ADC1 Input Channel 1, 2, 3 Select Register
• Register 19-5: AD1CHS0: ADC1 INPUT Channel 0 select Register
• Register 19-6: AD1CSSL: ADC1 Input Scan Select Register Low
(1,2,3)
• Register 19-7: AD1PCFGL: ADC1 Port Configuration Register Low
(1,2,3)
TABLE A-2: MAJOR SECTION UPDATES (CONTINUED)
Section Name Update Description

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