# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

- 1
- 2
…
- 229
- 230
- 231
- 232
- 233
…
- 501
- 502

© 2005-2011 Microchip Technology Inc. DS70157F-page 231
Section 5. Instruction Descriptions
Instruction
Descriptions
5
Description: Initiate a no overhead hardware DO loop, which is executed (lit14 + 1)
times. The DO loop begins at the address following the DO instruction, and
ends at the address 2 * Slit16 instruction words away. The 14-bit count
value (lit14) supports a maximum loop count value of 16384, and the 16-bit
offset value (Slit16) supports offsets of 32K instruction words in both
directions.
When this instruction executes, DCOUNT, DOSTART and DOEND are first
PUSHed into their respective shadow registers, and then updated with the
new DO loop parameters specified by the instruction. The DO level count,
DL<2:0> (CORCON<8:10>), is then incremented. After the DO loop
completes execution, the PUSHed DCOUNT, DOSTART and DOEND
registers are restored, and DL<2:0> is decremented.
The ‘k’ bits specify the loop count.
The ‘n’ bits are a signed literal that specifies the number of instructions that
are offset from the PC to the last instruction executed in the loop.
Special Features, Restrictions:
The following features and restrictions apply to the DO instruction.
1. Using a loop count of ‘0’ will result in the loop being executed one
time.
2. Using a loop size of -2, -1 or 0 is invalid. Unexpected results may
occur if these offsets are used.
3. The very last two instructions of the DO loop cannot be:
• an instruction which changes program control flow
• a DO or REPEAT instruction
Unexpected results may occur if any of these instructions are used.
4. If a hard trap occurs in the second to last instruction or third to last
instruction of a DO loop, the loop will not function properly. The hard
trap includes exceptions of priority level 13 through level 15,
inclusive.
Note 1: The DO instruction is interruptible and supports 1 level of
hardware nesting. Nesting up to an additional 5 levels may be
provided in software by the user. See the specific device family
reference manual for details.
2: The linker will convert the specified expression into the offset to
be used.
Words: 2
Cycles: 2
Example 1:
002000 LOOP6: DO #5, END6; Initiate DO loop (6 reps)
002004 ADD W1, W2, W3; First instruction in loop
002006 . . .
002008 . . .
00200A END6: SUB W2, W3, W4; Last instruction in loop
00200C . . .
Before
Instruction
After
Instruction
PC 00 2000 PC 00 2004
DCOUNT 0000 DCOUNT 0005
DOSTART FF FFFF DOSTART 00 2004
DOEND FF FFFF DOEND 00 200A
CORCON 0000 CORCON 0100 (DL = 1)
SR 0001 (C = 1) SR 0201 (DA, C = 1)

- 1
- 2
…
- 229
- 230
- 231
- 232
- 233
…
- 501
- 502