# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Interrupts

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© 2006 Microchip Technology Inc. Advance Information DS39707A-page 8-7
Section 8. Interrupts
Interrupts
8
Note that if the DISICNT register is zero, interrupts cannot be disabled by simply writing a
non-zero value to the register. Interrupts must first be disabled by using the DISI instruction.
Once the DISI instruction has executed and DISICNT holds a non-zero value, the interrupt
disable time can be extended by modifying the contents of DISICNT.
The DISI status bit (INTCON2<14>) is set whenever interrupts are disabled as a result of the
DISI instruction.
8.2.4 Interrupt Operation
All interrupt event flags are sampled during each instruction cycle. A pending Interrupt Request
(IRQ) is indicated by the flag bit being equal to a ‘1’ in an IFSn register. The IRQ will cause an
interrupt to occur if the corresponding bit in the Interrupt Enable (IECn) registers is set. For the
rest of the instruction cycle in which the IRQ is sampled, the priorities of all pending interrupt
requests are evaluated.
No instruction will be aborted when the CPU responds to the IRQ. The instruction that was in
progress when the IRQ is sampled will be completed before the ISR is executed.
If there is a pending IRQ with a user-assigned priority level greater than the current processor
priority level, indicated by the IPL<2:0> status bits (SR<7:5>), an interrupt will be presented to
the processor. The processor then saves the following information on the software stack:
• the current PC value
• the low byte of the processor STATUS register (SRL)
• the IPL3 status bit (CORCON<3>)
These three values that are saved on the stack allow the return PC address value, MCU status
bits and the current processor priority level to be automatically saved.
After the above information is saved on the stack, the CPU writes the priority level of the pending
interrupt into the IPL<2:0> bit locations. This action will disable all interrupts of less than, or equal
priority, until the Interrupt Service Routine (ISR) is terminated using the RETFIE instruction.
Figure 8-2: Stack Operation for Interrupt Event
Note: Software modification of the DISICNT register is not recommended.
Note: The DISI instruction can be used to quickly disable all user interrupt sources if no
source is assigned to CPU priority level 7.
<Free Word>
PC<15:0>
PC<22:16>
015
W15 (before IRQ)
W15 (after IRQ)
Stack Grows Towards
Higher Address
SR<7:0>
This stack location used
to store the IPL3 status
bit (CORCON<3>).

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