# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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 2007-2014 Microchip Technology Inc. DS70000195F-page 37
Inter-Integrated Circuit™ (I
2
C™)
7.0 COMMUNICATING AS A SLAVE
In some systems, particularly where multiple processors communicate with each other, the
dsPIC33/PIC24 device can communicate as a slave, as illustrated in Figure 7-1. When the I
2
C
module is enabled, the slave is active. The slave cannot initiate a message; it can only respond
to a message sequence initiated by a master. The master requests a response from a particular
slave as defined by the device address byte in the I
2
C protocol. The slave replies to the master
at the appropriate times as defined by the protocol.
As with the master module, sequencing the components of the protocol for the reply is a user
software task. However, the slave detects when the device address matches the address
specified by the user software for that slave.
Figure 7-1: A Typical Slave I
2
C™ Message: Multiprocessor Command/Status
After a Start condition, the slave receives and checks the device address. The slave can specify
either a 7-bit address or a 10-bit address. When a device address is matched, the module will
generate an interrupt to notify the user software that its device is selected. Based on the R/W
status bit sent by the master, the slave either receives or transmits data. If the slave is to receive
data, the slave automatically generates the Acknowledge (ACK
), loads the I2CxRCV register
with the received value currently in the I2CxRSR register and notifies the user software through
an interrupt. If the slave is to transmit data, the user software must load the I2CxTRN register.
7.1 Sampling Receive Data
All the incoming bits are sampled with the rising edge of the clock (SCLx) line.
7.2 Detecting Start and Stop Conditions
The slave detects the Start and the Stop conditions on the bus and indicates that status on the S
status bit (I2CxSTAT<3>) and P status bit (I2CxSTAT<4>). The Start (S) and Stop (P) status bits
are cleared when a Reset occurs or when the module is disabled. After detection of a Start or
Repeated Start event, the S status bit is set and the P status bit is cleared. After detection of a
Stop event, the P status bit is set and the S status bit is cleared.
7.2.1 INTERRUPT ON START/REPEATED START AND STOP CONDITIONS
(SLAVE MODE)
The user software is notified through a slave interrupt if the SCIE bit (I2CxCONH<5>) is set for
a Start/Repeated Start condition or if the PCIE bit (I2CxCONH<6>) is set for a Stop condition.
Bus
Master
SDAx
Start
First
Address
Address
Byte
S 1 1 1 0
A A
0
9 8
R P
Slave
SDAx
Activity
N
AAAA
Output
Output
R/W
ACK
ACK
ACK
Restart
R/W
ACK
NACK
Stop
1
Byte
Second
Address
Byte
A A
7 6
A A
5 4
A A
3 2
A A
1 0
Command
Data
Byte
1 1 1 0
A A
1
9 8
1
Status
Data
Byte
10-Bit
Address
R
Note: The PCIE and the SCIE bits are not available on all devices. Refer to the specific
device data sheet for availability.

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