# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 10 © 2005-2011 Microchip Technology Inc.
2.1 16-BIT MCU AND DSC CORE ARCHITECTURE OVERVIEW
This section provides an overview of the 16-bit architecture features and capabilities for the
following families of devices:
• 16-bit Microcontrollers (MCU):
- PIC24F
- PIC24H
- PIC24E
• 16-bit Digital Signal Controllers (DSC):
- dsPIC30F
- dsPIC33F
- dsPIC33E
2.1.1 Features Specific to 16-bit MCU and DSC Core
The core of the 16-bit MCU and DSC devices is a 16-bit (data) modified Harvard architecture with
an enhanced instruction set. The core has a 24-bit instruction word, with an 8-bit Op code field.
The Program Counter (PC) is 23 bits wide and addresses up to 4M x 24 bits of user program
memory space. An instruction prefetch mechanism is used to help maintain throughput and
provides predictable execution. The majority of instructions execute in a single cycle.
2.1.1.1 REGISTERS
The 16-bit MCU and DSC devices have sixteen 16-bit working registers. Each of the working
registers can act as a data, address or offset register. The 16th working register (W15) operates
as a software Stack Pointer for interrupts and calls.
2.1.1.2 INSTRUCTION SET
The instruction set is almost identical for the 16-bit MCU and DSC architectures. The instruction
set includes many Addressing modes and was designed for optimum C compiler efficiency.
2.1.1.3 DATA SPACE ADDRESSING
The data space can be addressed as 32K words or 64 Kbytes. The upper 32 Kbytes of the data
space memory map can optionally be mapped into program space at any 16K program word
boundary, which is a feature known as Program Space Visibility (PSV). The program to data
space mapping feature lets any instruction access program space as if it were the data space,
which is useful for storing data coefficients.
2.1.1.4 ADDRESSING MODES
The core supports Inherent (no operand), Relative, Literal, Memory Direct, Register Direct,
Register Indirect, and Register Offset Addressing modes. Each instruction is associated with a
predefined Addressing mode group, depending upon its functional requirements. As many as
seven Addressing modes are supported for each instruction.
For most instructions, the CPU is capable of executing a data (or program data) memory read, a
working register (data) read, a data memory write and a program (instruction) memory read per
instruction cycle. As a result, 3-operand instructions can be supported, allowing A + B = C
operations to be executed in a single cycle.
Note: Some devices families support Extended Data Space (EDS) addressing. See the
specific device data sheet and family reference manual for more details on this
feature.

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