# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004

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 2010-2013 Microchip Technology Inc. DS39881E-page 189
PIC24FJ64GA004 FAMILY
20.0 PROGRAMMABLE CYCLIC
REDUNDANCY CHECK (CRC)
GENERATOR
The programmable CRC generator offers the following
features:
 User-programmable polynomial CRC equation
 Interrupt output
 Data FIFO
The module implements a software configurable CRC
generator. The terms of the polynomial and its length
can be programmed using the X<15:1> bits
(CRCXOR<15:1>) and the PLEN<3:0> bits
(CRCCON<3:0>), respectively.
Consider the following equation:
EQUATION 20-1: CRC POLYNOMIAL
To program this polynomial into the CRC generator,
the CRC register bits should be set as shown in
Table 20-1.
TABLE 20-1: EXAMPLE CRC SETUP
Note that for the value of X<15:1>, the 12th bit and the
5th bit are set to 1, as required by the equation. The
0 bit, required by the equation, is always XORed. For a
16-bit polynomial, the 16th bit is also always assumed
to be XORed; therefore, the X<15:1> bits do not have
the 0 bit or the 16th bit.
A simplified block diagram of the module is shown in
Figure 20-1. The general topology of the shift engine is
shown in Figure 20-2.
FIGURE 20-1: CRC BLOCK DIAGRAM
Note: This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
“Programmable Cyclic Redundancy
Check (CRC)” (DS39714).
Bit Name Bit Value
PLEN<3:0> 1111
X<15:1> 000100000010000
x
16
+ x
12
+ x
5
+ 1
Variable FIFO
(8x16 or 16x8)
CRCDAT
CRC Shift Engine
CRCWDAT
FIFO Empty Event
Set CRCIF
Shift Clock (2 F
CY)

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