# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Reset

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© 2011 Microchip Technology Inc. DS39712D-page 7-3
Section 7. Reset
Reset
7
Register 7-1: RCON: Reset Control Register
(1)
R/W-0 R/W-0 U-0 R/W-0 U-0 R/C-0 U-0 R/W-0
TRAPR IOPUWR — LVREN
(2)
— DPSLP
(2)
CM PMSLP
(2,3)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1
EXTR SWR SWDTEN
(4)
WDTO SLEEP IDLE BOR POR
bit 7 bit 0
Legend: C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 TRAPR: Trap Reset Flag bit
1 = A Trap Conflict Reset has occurred
0 = A Trap Conflict Reset has not occurred
bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1 = An illegal opcode detection, an illegal address mode or an uninitialized W register used as an
Address Pointer caused a Reset
0 = An illegal opcode or uninitialized W Reset has not occurred
bit 13 Unimplemented: Read as ‘0’
bit 12 LVREN: Low-Voltage Regulator Enabled
(2)
1 = Regulated voltage supply provided solely by the low-voltage regulator during Sleep
0 = Regulated voltage supply provided by the main voltage regulator during Sleep
bit 11 Unimplemented: Read as ‘0’
bit 10 DPSLP: Program Memory Power During Sleep bit
(2)
1 = Deep Sleep has occurred
0 = Deep Sleep has not occurred
bit 9 CM: Configuration Mismatch Flag bit
1 = A Configuration Mismatch Reset has occurred
0 = A Configuration Mismatch Reset has not occurred
bit 8 PMSLP: Program Memory Power During Sleep Control bit
(2,3)
1
= Program memory bias voltage remains powered during Sleep
0
= Program memory bias voltage is powered down during Sleep; voltage regulator enters Standby mode
bit 7 EXTR: External Reset (MCLR) Pin bit
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
bit 6 SWR: Software Reset (Instruction) Flag bit
1 = A RESET instruction has been executed
0 = A RESET instruction has not been executed
Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: Implemented on select PIC24F devices only; otherwise, unimplemented and read as ‘0’.
3: This bit is named VREGS in some earlier PIC24F devices, with a different description of the bit’s
functionality. Regardless of the name or description, its function in power reduction is identical in all
devices.
4: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting. In devices with FWDTEN<1:0>, SWDTEN is only enabled when FWDTEN is ‘01’.
Consult the specific device family data sheet for more information.

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