# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Oscillator

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PIC24F Family Reference Manual
DS39700C-page 6-34 © 2009 Microchip Technology Inc.
6.17 REVISION HISTORY
Revision A (September 2006)
This is the initial released revision of this document.
Revision B (February 2008)
Expansion to include PIC24F devices in the GA1 and GB1 families. Made the following revisions:
• Updated Figure 6-1 to reflect new clock topology.
• Updated registers in Section 6.2 “CPU Clocking Scheme” to reflect new clock functionality.
• Replaced Section 6.6 “4x PLL” with new Section 6.6 “Phase Lock Loop (PLL)
Branch”. Added separate sections on 4x PLL and USB PLL block.
Added new Section 6.13 “Reference Clock Output Generator”. Previous Section 6.13 and
subsequent sections are renumbered as Section 6.14 and following.
Revision C (August 2009)
Added Section 6.4.5 “Clock Divider Register 2 (CLKDIV2)”. Appended to Section 6.4.2
“Clock Divider Register (CLKDIV)”. Added bits 5 and 4 to Register 6-2. Modified
Section 6.6.2 “96 MHz PLL Block”. Replaced Figure 6-8 with new diagram. Added
Section 6.6.3 “Considerations for Using the PLL Block”. Modified Table 6-6.

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