# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 -- UART

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dsPIC33/PIC24 Family Reference Manual
DS70000582E-page 16  2009-2013 Microchip Technology Inc.
On a device Reset, the UxTX pin is configured as an input; therefore, the state of the UxTX pin
is undefined. When the UART module is enabled, the transmit pin is driven high. It remains in
this state until data is written to the transmit buffer (UxTXREG). The transmit pin is driven low as
soon as the first data is written to the UxTXREG register. To ensure the Start bit detection, it is
recommended to have a delay between enabling the UARTx (UARTEN = 1) and initiating the first
transmission. The delay is baud rate dependent and should be equal to, or longer than, the time
it takes to transmit one data bit.
Figure 5-2: UARTx Transmission
5.1 Transmit Buffer (UxTXREG)
The transmit buffer is 9 bits wide and 4 levels deep. Along with the UARTx Transmit Shift Register
(UxTSR), the user effectively has a 5-level deep buffer. It is organized as a First-In First-Out
(FIFO). Once the UxTXREG contents are transferred to the UxTSR register, the current buffer
location becomes available for new data to be written and the next buffer location is sourced to
the UxTSR register. The UTXBF (UxSTA<9>) status bit is set whenever the buffer is full. If a user
application attempts to write to a full buffer, the new data will not be accepted into the FIFO.
The FIFO is reset during any device Reset, but is not affected when the device enters a power-saving
mode or wakes up from a power-saving mode.
5.2 Transmit Interrupt
The UARTx Transmit Interrupt Flag bit (UxTXIF) is located in the corresponding Interrupt Flag
Status (IFS) register. The UTXISEL<1:0> control bits (UxSTA<15,13>) determine when the
UART will generate a transmit interrupt.
 If UTXISEL<1:0> = 00, the UxTXIF bit is set when a character is transferred from the
transmit buffer to the UARTx Transmit Shift Register (UxTSR) or the transmit buffer is
empty. This implies at least one location is empty in the transmit buffer.
 If UTXISEL<1:0> = 01, the UxTXIF bit is set when the last character is shifted out of the
UxTSR register. This implies that all the transmit operations are completed.
 If UTXISEL<1:0> = 10, the UxTXIF bit is set when the character is transferred to the
UxTSR register and the transmit buffer is empty.
The UxTXIF bit is set when the module is first enabled. The user application should clear the
UxTXIF bit in the Interrupt Service Routine (ISR).
Switching between the two interrupt modes during operation is possible.
While the UxTXIF flag bit indicates the status of the UxTXREG register, the TRMT bit
(UxSTA<8>) indicates the status of the UxTSR. The TRMT status bit is a read-only bit, which is
set when the UxTSR is empty. No interrupt logic is tied to this bit, so the user application has to
poll this bit to determine if the UxTSR is empty.
Note: When the UTXEN bit is set, the UxTXIF flag bit will also be set regardless of the
UTXISEL bits (UxSTA<15,13>) settings.
UxTX
1 2
B0 B1 B2 B3 B4 B5 B6 B7
Bit Time = T
Software
Delay
1. The UARTx module is enabled (UARTEN = 1).
2. Data is written to the transmit buffer (UxTXREG) to begin the transmission.

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