# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Reset

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© 2011 Microchip Technology Inc. DS39712D-page 7-17
Section 7. Reset
Reset
7
The Reset time line, displayed in Figure 7-6, is similar to that displayed in Figure 7-5, except that
the PLL has been enabled, which increases the oscillator stabilization time.
The FSCM, if enabled, will begin to monitor the system clock after T
FSCM expires. Figure 7-6
displays that the oscillator and PLL delays expire before the FSCM is enabled. However, it is
possible that these delays may not expire until after FSCM is enabled. If a valid clock source is
not available at this time, the device will automatically switch to the FRC oscillator and a clock
failure trap will be generated. The user can switch to the desired crystal oscillator in the TSR.
Figure 7-6: Device Reset Delay, Crystal (XT/HS/SOSC) + PLL Clock Source
POR Circuit Threshold Voltage
Internal Power-on Reset Pulse
TPOR
(2)
T
OST
(5)
VDD
Oscillator Released
POR
System Reset Released
Note 1: Delay times shown are not drawn to scale.
2: T
POR = Power-on Reset delay.
3: T
STARTUP = TVREG if the on-chip regulator is enabled or TPWRT if it is disabled.
4: T
RST = Internal State Reset time.
5: T
OST = Oscillator Start-up Timer (OST). A 10-bit counter counts 1024 oscillator periods before releasing the
oscillator clock to the system.
6: T
LOCK is not inserted when PLL is disabled.
OSC Delay
(1)
T STARTUP
(3)
T RST
(4)
SYSRST
(1)
TLOCK
(6)
to System

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