# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Reset

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© 2011 Microchip Technology Inc. DS39712D-page 7-23
Section 7. Reset
Reset
7
7.19 REVISION HISTORY
Revision A (September 2006)
This is the initial released revision of this document.
Revision B (October 2008, not released)
Added Configurable BOR section.
Added material on Deep Sleep functionality and device Resets.
Revision C (March 2010)
Removed material on configurable BOR; this material has been incorporated into Section 40,
“Reset with Programmable BOR” of the “PIC24F Family Reference Manual” (DS39728).
Removed all references to the Fail-Safe Clock Monitor and its role in device Resets.
Updated Section 7.3 “Power-on Reset (POR)” with a corrected description of the POR start-up
sequence.
Replaced Figures 7-2, 7-5, 7-6, 7-7 and 7-8 with new start-up sequence diagrams.
Updated Tables 7-2 and 7-4 with new versions.
Other minor typographic corrections throughout the chapter.
Revision D (April 2011)
Added Register 7-2 RCON2 (Reset and System Control Register 2).
Added Section 7.7.1 “Voltage Regulator Tracking Mode and Low-Voltage Detection”.
Added Section 7.12 “V
BAT Mode”, Section 7.12.1 “VBAT”, Section 7.12.2 “VBPOR”,
Section 7.12.3 “V
DDPOR” and Section 7.12.4 “VDDBOR”.
Added Section 7.13.1 “V
BAT/Deep Sleep Status Bit Decoding”.
Replaced Table 7-2 with a new version that includes VBAT, VBPOR, VDDPOR and VDDBOR
status bits.
Added Table 7-3: V
BAT and Reset Flag Bit Operation.
Other typographical corrections throughout the chapter.

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