# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004

- 1
- 2
…
- 165
- 166
- 167
- 168
- 169
…
- 277
- 278

 2010-2013 Microchip Technology Inc. DS39881E-page 167
PIC24FJ64GA004 FAMILY
18.0 PARALLEL MASTER PORT
(PMP)
The Parallel Master Port (PMP) module is a parallel
8-bit I/O module, specifically designed to communicate
with a wide variety of parallel devices, such as commu-
nication peripherals, LCDs, external memory devices
and microcontrollers. Because the interface to parallel
peripherals varies significantly, the PMP is highly
configurable.
Key features of the PMP module include:
 Up to 16 Programmable Address Lines
 One Chip Select Line
 Programmable Strobe Options:
- Individual Read and Write Strobes or;
- Read/Write
Strobe with Enable Strobe
 Address Auto-Increment/Auto-Decrement
 Programmable Address/Data Multiplexing
 Programmable Polarity on Control Signals
 Legacy Parallel Slave Port Support
 Enhanced Parallel Slave Support:
- Address Support
- 4-Byte Deep Auto-Incrementing Buffer
 Programmable Wait States
 Selectable Input Voltage Levels
FIGURE 18-1: PARALLEL MASTER PORT (PMP) MODULE OVERVIEW
Note: This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
“Parallel Master Port (PMP)” (DS39713).
Note: A number of the pins for the PMP are not
present on PIC24FJ64GA004 devices.
Refer to the specific devices pinout to
determine which pins are available.
PMA<0>
PMBE
PMRD
PMWR
PMD<7:0>
PMENB
PMRD/PMWR
PMCS1
PMA<1>
PMA<10:2>
PMALL
PMALH
PMA<7:0>
PMA<15:8>
EEPROM
Address Bus
Data Bus
Control Lines
PIC24F
LCD
FIFO
Microcontroller
8-Bit Data
Up to 11-Bit Address
Parallel Master Port
Buffer
Note 1: PMA<10:2> are not available on 28-pin devices.
(1)

- 1
- 2
…
- 165
- 166
- 167
- 168
- 169
…
- 277
- 278