# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Oscillator

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PIC24F Family Reference Manual
DS39700C-page 6-12 © 2009 Microchip Technology Inc.
6.4.5 Clock Divider Register 2 (CLKDIV2)
The Clock Divider 2 register (Register 6-5) is provided to PIC24F devices that have a graphics con-
troller module. This register controls the frequency of the clock input to the display module interface
in the display controller. The frequency selection is controlled by writing to the selector bits
(GCLKDIV<6:0>). To cover the various frequency range of different displays, the clock division
starts from a divide-by-1 value, incrementing initially by 0.25. Half way through the 128 possible
values, the clock increases to 0.50, then after 32 values, increases to 1. The range covered for a
96 MHz input is from 1.5 MHz to 96 MHz, and for 48 MHz input, from 750 kHz to 48 MHz.
Register 6-5: CLKDIV2: Clock Divider Register 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
GCLKDIV6
(1)
GCLKDIV5
(1)
GCLKDIV4
(1)
GCLKDIV3
(1)
GCLKDIV2
(1)
GCLKDIV1
(1)
GCLKDIV0
(1)
—
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at all Resets ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-9 GCLKDIV<6:0>: Display Module Interface Clock Divider Selection bits
(1)
Values are based on a 96 MHz clock source set by G1CLKSEL (CLKDIV<4>) = 1. When the 48 MHz
clock source is selected, G1CLKSEL (CLKDIV<4>) = 1, all values are divided by 2.
0000000 = (0) 96.00 MHz (divide-by-1)
0000001 = (1) 76.80 MHz (divide-by-1.25); from here increment the divisor by 0.25
0000010 = (2) 64.00 MHz (divide-by-1.5)
0000011 = (3) 54.86 MHz (divide-by-1.75)
.
.
.
0111111 = (63) 5.73 MHz (divide-by-16.75)
1000000 = (64) 5.65 MHz (divide-by-17.00); from here increment the divisor by 0.50
1000000 = (65) 5.49 MHz (divide-by-17.50)
.
.
.
1011111 = (95) 2.95 MHz (divide-by-32.50)
1100000 = (96) 2.91 MHz (divide-by-33); from here increment the divisor by 1
1100001 = (97) 2.82 MHz (divide-by-34)
.
.
.
1111110 = (126) 1.52 MHz (divide-by-63)
1111111 = (127) 1.50 MHz (divide-by-64)
bit 8-0 Unimplemented: Read as ‘0’
Note 1: These bits take effect only when the 96 MHz PLL is enabled.

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