# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 -- Serial Peripheral Interface

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dsPIC33/PIC24 Family Reference Manual
DS70005185A-page 36  2014 Microchip Technology Inc.
6.0 SPI OPERATION IN POWER-SAVING MODES
The
dsPIC33/PIC24
families of devices have three power modes, which consist of normal (Full-
Power) mode and two power-saving modes invoked by the PWRSAV instruction. Depending on
the SPI mode selected, the entry into a power-saving mode may also affect the operation of the
module.
6.1 Sleep Mode
When the device enters Sleep mode, the system clock is disabled. The consequences of
entering Sleep mode depend on the mode (Master or Slave) on which the module was configured
at the time Sleep mode is invoked.
6.1.1 MASTER MODE OPERATION
The following are the effects of entering Sleep mode when the SPIx module is configured for
Master mode operation:
• The SPI clock generator in the SPIx module stops and is reset.
• The transmitter and receiver stop in Sleep mode. The transmitter or receiver will not
continue with a partially completed transmission at wake-up.
• If the SPIx module enters Sleep mode in the middle of a transmission or reception, the
transmission or reception is aborted. Because there is no automatic way to prevent an
entry into Sleep mode if a transmission or reception is pending, the user application must
synchronize entry into Sleep mode with the SPIx module operation to avoid aborted
transmissions.
6.1.2 SLAVE MODE OPERATION
As the clock pulses at the SCKx pin are externally provided for Slave mode, the module
continues to function in Sleep mode. It completes any transactions during the transition into
Sleep mode. On completion of a transaction, the SPIRBF flag is set. Consequently, the SPIxIF
bit is set.
If SPIx interrupts are enabled (SPIxIE = 1), the device wakes up from Sleep. If the SPIx Interrupt
Priority Level (IPL) is greater than the present CPU priority level, code execution resumes at the
SPIx interrupt vector location. Otherwise, code execution continues with the instruction following
the PWRSAV instruction that previously invoked Sleep mode. The module is not reset on entering
Sleep mode if it is operating as a slave device.
The register contents are not affected when the SPIx module is going into, or coming out of,
Sleep mode.
6.2 Idle Mode
When the device enters Idle mode, the system clock sources remain functional. The SPISIDL bit
(SPIxSTAT<13>) determines whether the module stops in Idle mode or continues to operate in
Idle mode.
If SPISIDL = 1, the SPIx module stops communication on entering Idle mode. It operates in the
same manner as it does in Sleep mode. If SPISID = 0 (default selection), the module continues
operation in Idle mode.

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