# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Family Data Sheet

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© 2011-2012 Microchip Technology Inc. Preliminary DS39997C-page 203
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
REGISTER 19-7: AD1PCFGL: ADC1 PORT CONFIGURATION REGISTER LOW
(1,2,3)
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PCFG15
(4,5)
— — PCFG12
(4,5)
PCFG11
(4,5)
PCFG10
(4,7)
PCFG9
(4,7)
PCFG8
(4,5)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PCFG
(4,5)
PCFG6
(4,5)
PCFG5
(4,6)
PCFG4
(4,6)
PCFG3
(4)
PCFG2
(4)
PCFG1
(4)
PCFG0
(4)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PCFG15: ADC Port Configuration Control bit
1 = Select ANx for input scan
0 = Skip ANx for input scan
bit 14-13 Unimplemented: Read as ‘0’
bit 12-0 PCFG12:PCFG0: ADC Port Configuration Control bits
(4)
1 = Port pin in Digital mode, port read input enabled, ADC input multiplexer connected to AV SS
0 = Port pin in Analog mode, port read input disabled, ADC samples pin voltage
Note 1: On devices without 14 analog inputs, all PCFG bits are R/W by user. However, PCFG bits are ignored on
ports without a corresponding input on device.
2: PCFGx = ANx, where x = 0 through 12, and 15.
3: PCFGx bits have no effect if the ADC module is disabled by setting ADxMD bit in the PMDx register. When
the bit is set, all port pins that have been multiplexed with ANx will be in Digital mode.
4: Pins shared with analog functions (i.e., ANx), are analog by default and therefore, must be set by the user
to enable any digital function on that pin. Reading any port pin with the analog function enabled will return
a ‘0’, regardless of the signal input level.
5: This setting is available in the dsPIC33FJ32(GP/MC)104 devices only, and is Reserved in all other
devices.
6: This setting is available on all devices excluding the dsPIC33FJXX(GP/MC)101, where it is Reserved.
7: This setting is available on all devices excluding the dsPIC33FJ16(GP/MC)101/102, where it is Reserved.

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