# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 106 © 2005-2011 Microchip Technology Inc.
ADDC
Add f to WREG with Carry
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} ADDC{.B} f {,WREG}
Operands: f ∈ [0 ... 8191]
Operation: (f) + (WREG) + (C) → destination designated by D
Status Affected: DC, N, OV, Z, C
Encoding: 1011 0100 1BDf ffff ffff ffff
Description: Add the contents of the default working register WREG, the contents of
the file register and the Carry bit and place the result in the destination
register. The optional WREG operand determines the destination
register. If WREG is specified, the result is stored in WREG. If WREG is
not specified, the result is stored in the file register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.
3: The Z flag is “sticky” for ADDC, CPB, SUBB and SUBBR. These
instructions can only clear Z.
Words: 1
Cycles:
1
(1)
Note 1:
In dsPIC33E and PIC24E devices, the listed cycle count does not apply to read and
read-modify-write operations on non-CPU Special Function Registers. For more
details, see
Note 3
in
Section 3.2.1 “Multi-Cycle Instructions”
.
Example 1:
ADDC.B RAM100 ; Add WREG and C bit to RAM100
; (Byte mode)
Before
Instruction
After
Instruction
WREG CC60 WREG CC60
RAM100 8006 RAM100 8067
SR 0001 (C=1) SR 0000
Example 2:
ADDC RAM200, WREG ; Add RAM200 and C bit to the WREG
; (Word mode)
Before
Instruction
After
Instruction
WREG 5600 WREG 8A01
RAM200 3400 RAM200 3400
SR 0001 (C=1) SR 000C (N, OV = 1)

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