# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- 10-Bit ADC

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PIC24F Family Reference Manual
DS39737A-page 49-6 Preliminary © 2010 Microchip Technology Inc.
Register 49-2: ADxCON2: ADCx Control Register 2
R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
VCFG2 VCFG1 VCFG0
— — CSCNA CHPS1 CHPS0
bit 15 bit 8
R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BUFS
— SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 VCFG<2:0>: Converter Voltage Reference Configuration bits
V
REFH = AVDD
V REFL = AVSS
bit 12-11 Unimplemented: Read as ‘0’
bit 10 CSCNA: Input Scan Select bit
1 = Scan inputs for CH0+ during Sample A bit
0 = Do not scan inputs
bit 9-8 CHPS<1:0>: Channel Select bits
When AD12B = 1, CHPS<1:0> is: U-0, Unimplemented, Read as ‘0’
1x =Converts CH0, CH1, CH2 and CH3
01 =Converts CH0 and CH1
00 =Converts CH0
bit 7 BUFS: Buffer Fill Status bit (only valid when BUFM = 1)
1 = ADC is currently filling the second half of the buffer. The user application should access data in the
first half of the buffer.
0 = ADC is currently filling the first half of the buffer. The user application should access data in the
second half of the buffer.
bit 6 Unimplemented: Read as ‘0’
bit 5-2 SMPI<3:0>: Sample and Conversion Operation bits
1111 =ADC interrupt is generated at the completion of every 16th sample/conversion operation
1110 =ADC interrupt is generated at the completion of every 15th sample/conversion operation
•
•
•
0001 =ADC interrupt is generated at the completion of every 2nd sample/conversion operation
0000 =ADC interrupt is generated at the completion of every sample/conversion operation
bit 1 BUFM: Buffer Fill Mode Select bit
1 = Starts filling the first half of the buffer on the first interrupt and the second half of the buffer on the
next interrupt
0 = Always starts filling the buffer from the start address
bit 0 ALTS: Alternate Input Sample Mode Select bit
1 = Uses channel input selects for Sample A on first sample and Sample B on next sample
0 = Always uses channel input selects for Sample A

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