# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Reset

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PIC24F Family Reference Manual
DS39712D-page 7-8 © 2011 Microchip Technology Inc.
7.3.1 Using the POR Circuit
To take advantage of the POR circuit, just tie the MCLR pin directly to VDD. This will eliminate
external RC components usually needed to create a POR delay. A minimum rise time for V
DD is
required. Refer to the “Electrical Characteristics” section of the specific device data sheet for
more information.
Depending on the application, a resistor may be required between the MCLR
pin and VDD. This
resistor can be used to decouple the MCLR
pin from a noisy power supply rail.
Figure 7-3 displays a possible POR circuit for a slow power supply ramp up. The external
POR circuit is only required if the device would exit Reset before the device V
DD is in the valid
operating range. The diode, D, helps discharge the capacitor quickly when V
DD powers down.
Figure 7-3: External Power-on Reset Circuit (for Slow V
DD Rise Time)
7.4 MCLR RESET
Whenever the MCLR pin is driven low, the device asynchronously asserts SYSRST, provided the
input pulse on MCLR
is longer than a certain minimum width, SY10 (see Section 7.16 “Electrical
Specifications”). When the MCLR
pin is released, SYSRST is also released. The Reset vector
fetch starts after the expiration of the T
RST delay, starting from the SYSRST release. The processor
continues to use the existing clock source that was in use before the MCLR
Reset occurred. The
EXTR status bit (RCON<7>) is set to indicate the MCLR
Reset.
7.5 SOFTWARE RESET INSTRUCTION (SWR)
Whenever the RESET instruction is executed, the device asserts SYSRST. This Reset state does
not re-initialize the clock. The clock source that is in effect prior to the RESET instruction remains
in effect. SYSRST
is released at the next instruction cycle, but the Reset vector fetch starts only
after the T
RST delay.
7.6 WATCHDOG TIMER RESET (WDTR)
Whenever a Watchdog Timer time-out occurs, the device asynchronously asserts SYSRST. The
clock source remains unchanged. Note that a WDT time-out during Sleep or Idle mode will wake-up
the processor, but NOT reset the processor. For more information, refer to Section 9. “Watchdog
Timer (WDT)” in the “PIC24F Family Reference Manual”.
Note 1: The value of R should be low enough so that the voltage drop across it does not violate the
V
IH specification of the MCLR pin.
2: R1 limits any current flowing into MCLR
from external capacitor, C, in the event of
MCLR
/VPP pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress
(EOS).
R1
(2)
MCLR
PIC24F
R
(1)
D
C
V
DD
VDD

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