# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- CPU

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© 2006 Microchip Technology Inc. Advance Information DS39703A-page 2-17
Section 2. CPU
CPU
2
2.7 COMPILER FRIENDLY ARCHITECTURE
The core architecture is designed to produce an efficient (code size and speed) C compiler.
• For most instructions, the core is capable of executing a data (or program data) memory
read, a working register (data) read, a data memory write and a program (instruction)
memory read per instruction cycle. As a result, 3 parameter instructions are supported,
allowing A + B = C operations to be executed in a single cycle.
• Instruction addressing modes are very flexible and are matched closely to compiler needs.
• There are sixteen, 16 x 16-bit working register arrays, each of which can act as data,
address or offset registers. One working register (W15) operates as a software stack for
interrupts and calls.
• Linear indirect access of all data space is supported, plus the memory direct address range
is extended to 8 Kbytes, with the addition of 16-bit direct address load and store
instructions.
• Linear indirect access of 32K word (64 Kbyte) pages within program space (user and test
space) is supported using any working register via new table read and write instructions.
• Part of the data space can be mapped into program space, allowing constant data to be
accessed as if it were in data space using PSV mode.
2.8 MULTI-BIT SHIFT SUPPORT
The PIC24F core supports single-cycle, multi-bit arithmetic and logic shifts using a shifter block.
It also supports single bit shifts through the ALU. The multi-bit shifter is capable of performing up
to a 15-bit arithmetic right shift, or up to a 15-bit left shift, in a single cycle.
A full summary of instructions that use the shift operation is provided below in Table 2-3.
Table 2-3: Instructions Using Single and Multi-Bit Shift Operations
All multi-bit shift instructions only support Register Direct Addressing mode for both the operand
source and result destination.
Instruction Description
ASR Arithmetic shift right source register by one or more bits.
SL Shift left source register by one or more bits.
LSR Logical shift right source register by one or more bits.

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