# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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© 2005-2011 Microchip Technology Inc. DS70157F-page 263
Section 5. Instruction Descriptions
Instruction
Descriptions
5
IOR
Inclusive OR Wb and Ws
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} IOR{.B} Wb, Ws, Wd
[Ws], [Wd]
[Ws++], [Wd++]
[Ws--], [Wd--]
[++Ws], [++Wd]
[--Ws], [--Wd]
Operands:
Wb ∈ [W0 ... W15]
Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]
Operation:
(Wb).IOR.(Ws) → Wd
Status Affected:
N, Z
Encoding:
0111 0www wBqq qddd dppp ssss
Description: Compute the logical inclusive OR operation of the contents of the source
register Ws and the contents of the base register Wb, and place the result in
the destination register Wd. Register direct addressing must be used for Wb.
Either register direct or indirect addressing may be used for Ws and Wd.
The ‘w’ bits select the address of the base register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
Words:
1
Cycles:
1
(1)
Note 1:
In dsPIC33E and PIC24E devices, the listed cycle count does not apply to read and
read-modify-write operations on non-CPU Special Function Registers. For more
details, see
Note 3
in
Section 3.2.1 “Multi-Cycle Instructions”
.
Example 1:
IOR.B W1, [W5++], [W9++] ; IOR W1 and [W5] (Byte mode)
; Store result to [W9]
; Post-increment W5 and W9
Before
Instruction
After
Instruction
W1 AAAA W1 AAAA
W5 2000 W5 2001
W9 2400 W9 2401
Data 2000 1155 Data 2000 1155
Data 2400 0000 Data 2400 00FF
SR 0000 SR 0008 (N = 1)

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