# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Interrupts

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PIC24F Family Reference Manual
DS39707A-page 8-20 Advance Information © 2006 Microchip Technology Inc.
8.5 INTERRUPT SETUP PROCEDURES
8.5.1 Initialization
The following steps describe how to configure a source of interrupt:
1. Set the NSTDIS Control bit (INTCON1<15>) if nested interrupts are not desired.
2. Select each user-assigned priority level for the interrupt source by writing the control bits in
the appropriate IPCn Control register. The priority level will depend on the specific
application and type of interrupt source. If multiple priority levels are not desired, the IPCn
register control bits for all enabled interrupt sources may be programmed to the same
non-zero value.
3. Clear the interrupt flag status bit associated with the peripheral in the associated IFSn Status
register.
4. Enable the interrupt source by setting the interrupt enable control bit associated with the
source in the appropriate IECn Control register.
8.5.2 Interrupt Service Routine
The method that is used to declare an ISR and initialize the IVT and AIVT with the correct vector
address will depend on the programming language (i.e., C or assembler) and the language
development toolsuite that is used to develop the application. In general, the user must clear the
interrupt flag in the appropriate IFSn register for the source of interrupt that the ISR handles.
Otherwise, the ISR will be re-entered immediately after exiting the routine. If the ISR is coded in
assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC
value, SRL value and old CPU priority level.
8.5.3 Trap Service Routine
A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag
in the INTCON1 register must be cleared to avoid re-entry into the TSR.
8.5.4 Interrupt Disable
All user interrupts can be disabled using the following procedure:
1. Push the current SR value onto the software stack using the PUSH instruction.
2. Force the CPU to priority level 7 by inclusive ORing the value 0xE0 with SRL.
To enable user interrupts, the POP instruction may be used to restore the previous SR value.
Note that only user interrupts with a priority level of 7 or less can be disabled. Trap sources
(level 8-level 15) cannot be disabled.
The DISI instruction provides a convenient way to disable interrupts of priority levels 1-6 for a
fixed period of time. Level 7 interrupt sources are not disabled by the DISI instruction.
Note: At a device Reset, the IPCn registers are initialized, such that all user interrupt
sources are assigned to priority level 4.

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