# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- CPU

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PIC24F Family Reference Manual
DS39703A-page 2-16 Advance Information © 2006 Microchip Technology Inc.
2.6.3 Divider
The PIC24F features both 32-bit/16-bit and 16-bit/16-bit signed and unsigned, integer divide
operations which are implemented as single instruction iterative divides.
The quotient for all divide instructions ends up in W0 and the remainder in W1. 16-bit signed and
unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W
register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one
cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number
of cycles to execute.
The divide instructions must be executed within a REPEAT loop. Any other form of execution
(e.g., a series of discrete divide instructions) will not function correctly because the instruction
flow function is conditional on RCOUNT. The divide flow does not automatically set up the
REPEAT, which must therefore, be explicitly executed with the correct operand value as shown
in Table 2-2 (REPEAT will execute the target instruction {operand value + 1} time).
Table 2-2: Divide Execution Time
All intermediate data is saved in W1:W0 after each iteration. The N, C and Z Status flags are used
to convey control information between iterations. Consequently, although the divide instructions
are listed as 19 cycle operations, the divide iterative sequence is interruptible, just like any other
REPEAT loop.
Dividing by zero will initiate an arithmetic error trap. The divisor is evaluated during the first cycle
of the divide instruction, so the first cycle will be executed prior to the start of exception processing
for the trap. Refer to Section 8. “Interrupts” for more details.
Instruction Description Iterations
REPEAT
Operand
Value
Total Execution
Time
(including REPEAT)
DIV.SD Signed divide:
W(m + 1):Wm/Wn → W0; Rem → W1
18 17 19
DIV.SW Signed divide:
Wm/Wn → W0; Rem → W1
18 17 19
DIV.UD Unsigned divide:
W(m + 1):Wm/Wn → W0; Rem → W1
18 17 19
DIV.UW Unsigned divide:
Wm/Wn → W0; Rem → W1
18 17 19

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