# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 -- Serial Peripheral Interface

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dsPIC33/PIC24 Family Reference Manual
DS70005185A-page 30  2014 Microchip Technology Inc.
Figure 3-12: SPIx Master/Framed Slave Timing (FRMDLY = 1)
3.5.4 SPI SLAVE/FRAMED MASTER MODE
In SPI Slave/Framed Master mode, the module acts as an SPIx slave and takes its clock from
the other SPIx module; however, it produces frame synchronization signals to control data
transmission (see Figure 3-13). It is enabled by setting the MSTEN bit (SPIxCON1<5>) to ‘0’, the
FRMEN bit (SPIxCON2<15>) to ‘1’ and the SPIFSD bit (SPIxCON2<14>) to ‘0’.
The SPIx input clock is continuous in Slave mode. The SSx
pin is an output pin when the SPIFSD
bit is low. Therefore, when the SPIxBUF register is written, the module drives the SSx
pin to the
active state, on the appropriate transmit edge of the SPIx clock, for one SPIx clock cycle. Data
starts transmitting on the appropriate SPIx clock transmit edge.
Figure 3-13: SPIx Slave/Framed Master Connection Diagram
SCKx
(CKP = 0)
bit 14 bit 13 bit 12
SDIx
bit 14 bit 13 bit 12
SCKx
(CKP = 1)
Write to SPIxBUF
Pulse Generated by SSx,
Receive Samples at SDIx
SSx
(FRMPOL = 1)
SSx
(FRMPOL = 0)
bit 15
bit 15
SDOx
SDOx
SDIx
dsPIC33/PIC24
Serial Clock
SSx
SCKx
Frame Sync
Pulse
SDIx
SDOx
PROCESSOR 2
SSx
SCKx
(SPIx Slave/Framed Master)

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