# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- CPU

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PIC24F Family Reference Manual
DS39703A-page 2-4 Advance Information © 2006 Microchip Technology Inc.
2.2 PROGRAMMER’S MODEL
The programmer’s model for the PIC24F is shown in Figure 2-2. All registers in the programmer’s
model are memory mapped and can be manipulated directly by instructions. A description of
each register is provided in Table 2-1.
All registers associated with the programmer’s model are memory mapped, as shown in Table 2-5.
Figure 2-2: Programmer’s Model
Table 2-1: Programmer’s Model Register Descriptions
Register(s) Name Description
W0 through W15 Working register array
PC 23-bit Program Counter
SR ALU STATUS register
SPLIM Stack Pointer Limit Value register
TBLPAG Table Memory Page Address register
PSVPAG Program Space Visibility Page Address register
RCOUNT Repeat Loop Counter register
CORCON CPU Control register
N OV Z C
TBLPAG
22
7
0
015
Program Counter
Data Table Page Address
STATUS Register
Working/Address
Registers
W0 (WREG)
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
Frame Pointer/W14
Stack Pointer/W15
PSVPAG
7
0
Program Space Visibility
RA
0
— — — —
RCOUNT
15
0
Repeat Loop Counter
IPL<2:0>
SPLIM
Stack Pointer Limit
SRL
PUSH.S and POP.S Shadows
0
0
— —
Page Address
—
DC
CORCON
15
0
Core Control Register
SRH
0

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