# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 -- Errata

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PIC24FJ64GA004 FAMILY
DS80000470H-page 2  2009-2013 Microchip Technology Inc.
TABLE 2: SILICON ISSUE SUMMARY
Module Feature
Item
Number
Issue Summary
Affected Revisions
(1)
A3/A4 B4 B5 B8
JTAG — 1. Persistent pull-up (RA3) when JTAG
disabled.
X
LVD — 2. No LVD interrupt with low-voltage condition
at Reset.
X
Core Idle mode 3. Clock failure trap fails in Idle mode. X
Core Doze mode 4. RAM read repeats on entering Doze mode. X
Core BOR 5. POR and BOR flags both set on BOR. X
Core RAM 6. RAM size implementation on some devices. X
A/D — 7. Unimplemented channels may be selected. X
A/D — 8. Missing midscale conversion code. X
A/D — 9. Device may not wake when convert on INT0
trigger is selected.
X
I
2
C SDA Line
State (I2C1)
10. Line state may not be detected correctly. X
UART — 11. Reception failures in High-Speed mode. X
UART — 12. Erroneous baud rate calculations in
High-Speed mode.
X
UART Auto-Baud 13. Double receive interrupt with auto-baud
reception.
X
UART Auto-Baud 14. Insertion of spurious data with auto-baud
reception.
X
UART Auto-Baud 15. Auto-baud calculation errors causing
transmit or receive failures.
X
UART Break
Character
Generation
16. The UARTx module will not generate
back-to-back Break characters.
X X X X
Output
Compare
— 17. Single missed compare events under certain
conditions.
X
SPI Enhanced
Buffer mode
18. Some flag bits are set at incorrect times in
Enhanced Buffer mode.
X
SPI — 19. Module in Slave mode may ignore SSx
pin
and receive data anyway.
X
SPI Enhanced
Buffer mode
20. No SPIx interrupt in Enhanced Buffer mode
under certain conditions.
X
I/O — 21. Spec change for V
OL and V OH. X
I/O — 22. OSCO/RA3 driven immediately following
POR.
X
JTAG — 23. Sync loss in ICSP™ mode. X
Note 1: Only those issues indicated in the last column apply to the current silicon revision.

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