# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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© 2005-2011 Microchip Technology Inc. DS70157F-page 23
Section 2. Programmer’s Model
Programmer’s
Model
2
2.16.4 DSP ALU Status Bits (dsPIC30F, dsPIC33F and dsPIC33E
Devices)
The high byte of the STATUS Register (SRH) is used by the DSP class of instructions, and it is
modified when data passes through one of the adders. The SRH provides status information
about overflow and saturation for both accumulators. The Saturate A, Saturate B, Overflow A and
Overflow B (SA, SB, OA, OB) bits provide individual accumulator status, while the Saturate AB
and Overflow AB (SAB, OAB) bits provide combined accumulator status. The SAB and OAB bits
provide an efficient method for the software developer to check the register for saturation or
overflow.
The OA and OB bits are used to indicate when an operation has generated an overflow into the
guard bits (bits 32 through 39) of the respective accumulator. This condition can only occur when
the processor is in Super Saturation mode, or if saturation is disabled. It indicates that the
operation has generated a number which cannot be represented with the lower 31 bits of the
accumulator. The OA and OB bits are writable in dsPIC33E devices.
The SA and SB bits are used to indicate when an operation has generated an overflow out of the
MSb of the respective accumulator. The SA and SB bits are active, regardless of the Saturation
mode (Disabled, Normal or Super) and may be considered “sticky”. Namely, once the SA or SB
bit is set to ‘1’, it can only be cleared manually by software, regardless of subsequent DSP
operations. When it is required, the BCLR instruction can be used to clear the SA or SB bit.
In addition, the SA and SB bits can be set by software in dsPIC33E devices, enabling efficient
context state switching.
For convenience, the OA and OB bits are logically ORed together to form the OAB flag, and the
SA and SB bits are logically ORed to form the SAB flag. These cumulative Status bits provide
efficient overflow and saturation checking when an algorithm is implemented. Instead of
interrogating the OA and the OB bits independently for arithmetic overflows, a single check of
OAB can be performed. Likewise, when checking for saturation, SAB may be examined instead
of checking both the SA and SB bits. Note that clearing the SAB flag will clear both the SA and
SB bits.
2.16.5 Interrupt Priority Level Status Bits
The three Interrupt Priority Level (IPL) bits of the SRL, SR<7:5>, and the IPL3 bit, CORCON<3>,
set the CPU’s IPL which is used for exception processing. Exceptions consist of interrupts and
hardware traps. Interrupts have a user-defined priority level between 0 and 7, while traps have a
fixed priority level between 8 and 15. The fourth Interrupt Priority Level bit, IPL3, is a special IPL
bit that may only be read or cleared by the user. This bit is only set when a hardware trap is
activated and it is cleared after the trap is serviced.
The CPU’s IPL identifies the lowest level exception which may interrupt the processor. The
interrupt level of a pending exception must always be greater than the CPU’s IPL for the CPU to
process the exception. This means that if the IPL is 0, all exceptions at priority Level 1 and above
may interrupt the processor. If the IPL is 7, only hardware traps may interrupt the processor.
When an exception is serviced, the IPL is automatically set to the priority level of the exception
being serviced, which will disable all exceptions of equal and lower priority. However, since the
IPL field is read/write, one may modify the lower three bits of the IPL in an Interrupt Service
Routine to control which exceptions may preempt the exception processing. Since the SRL is
stacked during exception processing, the original IPL is always restored after the exception is
serviced. If required, one may also prevent exceptions from nesting by setting the NSTDIS bit
(INTCON1<15>).
Note: For more detailed information on exception processing, refer to the family reference
manual of the specific device.

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