# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- I2C

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 2007-2014 Microchip Technology Inc. DS70000195F-page 55
Figure 7-14: Slave Message (Write Data to Slave: 7-Bit Address; Clock Stretching Enabled; A10M = 0; GCEN = 0; IPMIEN = 0;
STRICT = 0 and BOEN = 0)
1
User software sets the STREN bit to enable clock stretching.
SCLx (Master)
SDAx (Master)
SCLx (Slave)
SDAx (Slave)
I2CxTRN
TBF
I2CxRCV
RBF
SI2CxIF
STREN
1 2 3 4 5 6 7 8
A1A0
9
A
D7D6D5D4D3D2D1
1 2 3 4 5 6 7 8 9
32
A
5 3 8
2
Slave receives address byte. I2CxRCV register is read by user software to
Next received byte is message data. The byte moved to I2CxRCV register, sets RBF.
6
User software sets SCLREL bit to release clock.
7
Slave does not clear SCLREL because RBF = 0 at this
A6A5 A4A3 A2
S
P
I2COV
R/W
D/A
D7D6D5D4D3D2D1
1 2 3 4 5 6 7 8 9
A
D7D6D5 D3
1 2 3 4 5
SCLREL
5 9
D4
4 6 71
4
Because RBF = 1 at ninth clock, automatic clock stretch begins.
Slave clears SCLREL bit. Slave pulls SCLx line low to stretch clock.
5
User software reads I2CxRCV register. RBF bit clears.
8
User software may clear SCLREL to cause a clock hold. Mod
9
User software may set SCLREL to release a clock hold
low before asserting SCLx low.
prevent buffer overflow.
W
D0 D0
3

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