# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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© 2005-2011 Microchip Technology Inc. DS70157F-page 191
Section 5. Instruction Descriptions
Instruction
Descriptions
5
Example 2:
COM W0, [W1++] ; COM W0 and store to [W1] (Word mode)
; Post-increment W1
Before
Instruction
After
Instruction
W0 D004 W0 D004
W1 1000 W1 1002
Data 1000 ABA9 Data 1000 2FFB
SR 0000 SR 0000
CP
Compare f with WREG, Set Status Flags
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} CP{.B} f
Operands: f ∈ [0 ...8191]
Operation: (f) – (WREG)
Status Affected: DC, N, OV, Z, C
Encoding: 1110 0011 0B0f ffff ffff ffff
Description: Compute (f) – (WREG) and update the STATUS register. This instruction
is equivalent to the SUBWF instruction, but the result of the subtraction is
not stored.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.
Words: 1
Cycles:
1
(1)
Note 1:
In dsPIC33E and PIC24E devices, the listed cycle count does not apply to read and
read-modify-write operations on non-CPU Special Function Registers. For more
details, see
Note 3
in
Section 3.2.1 “Multi-Cycle Instructions”
.
Example 1:
CP.B RAM400 ; Compare RAM400 with WREG (Byte mode)
Before
Instruction
After
Instruction
WREG 8823 WREG 8823
RAM400 0823 RAM400 0823
SR 0000 SR 0003 (C = 1)
Example 2:
CP 0x1200 ; Compare (0x1200) with WREG (Word mode)
Before
Instruction
After
Instruction
WREG 2377 WREG 2377
Data 1200 2277 Data 1200 2277
SR 0000 SR 0008 (N = 1)

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