# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Family Data Sheet

- 1
- 2
…
- 215
- 216
- 217
- 218
- 219
…
- 349
- 350

© 2011-2012 Microchip Technology Inc. Preliminary DS39997C-page 217
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
REGISTER 20-6: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — VREFSEL BGSEL<1:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
CVREN CVROE
(1)
CVRR — CVR<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10 VREFSEL: Voltage Reference Select bit
1 = CV
REFIN = CV REF pin
0 = CV
REFIN is generated by the resistor network
bit 9-8 BGSEL<1:0>: Band Gap Reference Source Select bits
11 = INTREF = CV
REF pin
10 = INTREF = 1.2V (nominal)
(2)
0x = Reserved
bit 7 CVREN: Comparator Voltage Reference Enable bit
1 = Comparator voltage reference circuit powered on
0 = Comparator voltage reference circuit powered down
bit 6 CVROE: Comparator Voltage Reference Output Enable bit
(1)
1 = Voltage level is output on CV REF pin
0 = Voltage level is disconnected from CV REF pin
bit 5 CVRR: Comparator Voltage Reference Range Selection bit
1 = CV RSRC/24 step size
0 = CV RSRC/32 step size
bit 4 Unimplemented: Read as ‘0’
bit 3-0 CVR<3:0>: Comparator Voltage Reference Value Selection 0 ≤ CVR<3:0> ≤ 15 bits
When CVRR = 1:
CV REFIN = (CVR<3:0>/24) • (CV RSRC)
When CVRR =
0:
CV REFIN = 1/4 • (CV RSRC) + (CVR<3:0>/32) • (CVRSRC)
Note 1: CVROE overrides the TRIS bit setting.
2: This reference voltage is generated internally on the device. Refer to Section 26.0 “Electrical
Characteristics” for the specified voltage range.

- 1
- 2
…
- 215
- 216
- 217
- 218
- 219
…
- 349
- 350