# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 112 © 2005-2011 Microchip Technology Inc.
AND
AND f and WREG
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} AND{.B} f {,WREG}
Operands: f ∈ [0 ... 8191]
Operation: (f).AND.(WREG) → destination designated by D
Status Affected: N, Z
Encoding: 1011 0110 0BDf ffff ffff ffff
Description: Compute the logical AND operation of the contents of the default working
register WREG and the contents of the file register, and place the result in
the destination register. The optional WREG operand determines the
destination register. If WREG is specified, the result is stored in WREG.
If WREG is not specified, the result is stored in the file register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.
Words: 1
Cycles:
1
(1)
Note 1:
In dsPIC33E and PIC24E devices, the listed cycle count does not apply to read and
read-modify-write operations on non-CPU Special Function Registers. For more
details, see
Note 3
in
Section 3.2.1 “Multi-Cycle Instructions”
.
Example 1:
AND.B RAM100 ; AND WREG to RAM100 (Byte mode)
Before
Instruction
After
Instruction
WREG CC80 WREG CC80
RAM100 FFC0 RAM100 FF80
SR 0000 SR 0008 (N = 1)
Example 2:
AND RAM200, WREG ; AND RAM200 to WREG (Word mode)
Before
Instruction
After
Instruction
WREG CC80 WREG 0080
RAM200 12C0 RAM200 12C0
SR 0000 SR 0000

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