# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 -- Serial Peripheral Interface

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dsPIC33/PIC24 Family Reference Manual
DS70005185A-page 8  2014 Microchip Technology Inc.
Register 2-2: SPIXCON1: SPIx Control Register 1
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — DISSCK
(5)
DISSDO MODE16 SMP
(2)
CKE
(1)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SSEN
(4)
CKP MSTEN SPRE2
(3)
SPRE1
(3)
SPRE0
(3)
PPRE1
(3)
PPRE0
(3)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12 DISSCK: Disable SCKx Pin bit (SPI Master modes only)
(5)
1 = SPIx clock on SCKx pin is disabled; pin functions as I/O
0 = SPIx clock on SCKx pin is enabled
bit 11 DISSDO: Disable SDOx Pin bit
1 = SDOx pin is not used by the module; pin functions as I/O
0 = SDOx pin is controlled by the module
bit 10 MODE16: Word/Byte Communication Select bit
1 = Communication is word-wide (16 bits)
0 = Communication is byte-wide (8 bits)
bit 9 SMP: SPIx Data Input Sample Phase bit
(2)
Master mode:
1 = Input data is sampled at the end of data output time
0 = Input data is sampled at the middle of data output time
Slave mode:
The SMP bit must be cleared when the SPIx module is used in Slave mode.
bit 8 CKE: SPIx Clock Edge Select bit
(1)
1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6)
0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6)
bit 7 SSEN: Slave Select Enable bit (Slave mode)
(4)
1 = SSx pin is used for Slave mode
0 = SSx
pin is not used by the module; pin is controlled by port function
bit 6 CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
bit 5 MSTEN: Master Mode Enable bit
1 = Master mode
0 = Slave mode
Note 1: The CKE bit is not used in Framed SPI modes. Program this bit to ‘0’ for Framed SPI modes (FRMEN = 1).
2: The SMP bit must be set only after setting the MSTEN bit. The SMP bit remains clear if MSTEN = 0.
3: Do not set the primary and secondary prescalers to the value of 1:1 at the same time.
4: This bit must be cleared when FRMEN = 1.
5: If DISSCK = 1, the SCKx pin becomes a regular I/O and can be controlled using the TRISx and LATx reg-
isters, but internally, the SCKx clock may not be disconnected from the receiving part of the SPIx module
and the data will still be captured from the SDIx pin. To avoid an overflow error, the application may need
to read the SPIx buffer after the transmission.

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