# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 62 © 2005-2011 Microchip Technology Inc.
4.3 INSTRUCTION STALLS
In order to maximize the data space EA calculation and operand fetch time, the X data space
read and write accesses are partially pipelined. A consequence of this pipelining is that address
register data dependencies may arise between successive read and write operations using
common registers.
‘Read After Write’ (RAW) dependencies occur across instruction boundaries and are detected by
the hardware. An example of a RAW dependency would be a write operation that modifies W5,
followed by a read operation that uses W5 as an Address Pointer. The contents of W5 will not be
valid for the read operation until the earlier write completes. This problem is resolved by stalling
the instruction execution for one instruction cycle, which allows the write to complete before the
next read is started.
4.3.1 RAW Dependency Detection
During the instruction pre-decode, the core determines if any address register dependency is
imminent across an instruction boundary. The stall detection logic compares the W register
(if any) used for the destination EA of the instruction currently being executed with the W register
to be used by the source EA (if any) of the prefetched instruction. When a match between the
destination and source registers is identified, a set of rules are applied to decide whether or not
to stall the instruction by one cycle.
Table 4-6 lists various RAW conditions which cause an
instruction execution stall.
Table 4-6: Raw Dependency Rules (Detection By Hardware)
Destination
Address Mode
Using Wn
Source Address
Mode
Using Wn
Stall
Required?
Examples
(2)
(Wn = W2)
Direct Direct No Stall ADD.W W0, W1, W2
MOV.W W2, W3
Indirect Direct No Stall ADD.W W0, W1, [W2]
MOV.W W2, W3
Indirect Indirect No Stall ADD.W W0, W1, [W2]
MOV.W [W2], W3
Indirect Indirect with
pre/post-modification
No Stall ADD.W W0, W1, [W2]
MOV.W [W2++], W3
Indirect with
pre/post-modification
Direct No Stall ADD.W W0, W1, [W2++]
MOV.W W2, W3
Direct Indirect Stall
(1)
ADD.W W0, W1, W2
MOV.W [W2], W3
Direct Indirect with
pre/post-modification
Stall
(1)
ADD.W W0, W1, W2
MOV.W [W2++], W3
Indirect Indirect Stall
(1)
ADD.W W0, W1, [W2](2)
MOV.W [W2], W3(2)
Indirect Indirect with
pre/post-modification
Stall
(1)
ADD.W W0, W1, [W2](2)
MOV.W [W2++], W3(2)
Indirect with
pre/post-modification
Indirect Stall
(1)
ADD.W W0, W1, [W2++]
MOV.W [W2], W3
Indirect with
pre/post-modification
Indirect with
pre/post-modification
Stall
(1)
ADD.W W0, W1, [W2++]
MOV.W [W2++], W3
Note 1: When stalls are detected, one cycle is added to the instruction execution time.
2: For these examples, the contents of W2 = the mapped address of W2 (0x0004).

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