# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

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© 2005-2011 Microchip Technology Inc. DS70157F-page 299
Section 5. Instruction Descriptions
Instruction
Descriptions
5
MPY.N
Multiply -Wm by Wn to Accumulator
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X
Syntax: {label:} MPY.N Wm * Wn, Acc {,[Wx], Wxd} {,[Wy], Wyd}
{,[Wx] + = kx, Wxd} {,[Wy] + = ky, Wyd}
{,[Wx] – = kx, Wxd} {,[Wy] – = ky, Wyd}
{,[W9 + W12], Wxd} {,[W11 + W12], Wyd}
Operands: Wm * Wn ∈ [W4 * W5; W4 * W6; W4 * W7; W5 * W6; W5 * W7; W6 * W7]
Acc ∈ [A,B]
Wx ∈ [W8, W9]; kx ∈ [-6, -4, -2, 2, 4, 6]; Wxd ∈ [W4 ... W7]
Wy ∈ [W10, W11]; ky ∈ [-6, -4, -2, 2, 4, 6]; Wyd ∈ [W4 ... W7]
Operation: -(Wm) * (Wn) → Acc(A or B)
([Wx]) →Wxd; (Wx) + kx →Wx
([Wy]) → Wyd; (Wy) + ky → Wy
Status Affected: OA, OB, OAB
Encoding:
1100 0mmm A1xx yyii iijj jj11
Description: Multiply the contents of a working register by the negative of the contents
of another working register, optionally prefetch operands in preparation for
another MAC type instruction and optionally store the unspecified
accumulator results. The 32-bit result of the signed multiply is
sign-extended to 40 bits and stored to the specified accumulator.
The ‘m’ bits select the operand registers Wm and Wn for the multiply.
The ‘A’ bit selects the accumulator for the result.
The ‘x’ bits select the prefetch Wxd destination.
The ‘y’ bits select the prefetch Wyd destination.
The ‘i’ bits select the Wx prefetch operation.
The ‘j’ bits select the Wy prefetch operation.
Note 1: The IF bit (CORCON<0>), determines if the multiply is
fractional or an integer.
2: The US<1:0> bits (CORCON<13:12> in dsPIC33E,
CORCON<12> in dsPIC30F/dsPIC33F) determine if the
multiply is unsigned, signed, or mixed-sign. Only dsPIC33E
devices support mixed-sign multiplication.
Words: 1
Cycles: 1

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