# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ64GA004 - Programmers Reference Manual

- 1
- 2
…
- 72
- 73
- 74
- 75
- 76
…
- 501
- 502

16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 74 © 2005-2011 Microchip Technology Inc.
Figure 4-10: Stack After “CALL COMPUTE” Executes
Figure 4-11: Stack After “LNK #4” Executes
4.7.3 Stack Pointer Overflow
There is a Stack Limit register (SPLIM) associated with the Stack Pointer that is reset to 0x0000.
SPLIM is a 16-bit register, but SPLIM<0> is fixed to ‘0’, because all stack operations must be
word-aligned.
The stack overflow check will not be enabled until a word write to SPLIM occurs, after which time
it can only be disabled by a device Reset. All effective addresses generated using W15 as a
source or destination are compared against the value in SPLIM. Should the effective address be
greater than the contents of SPLIM, then a stack error trap is generated.
If stack overflow checking has been enabled, a stack error trap will also occur if the W15 effective
address calculation wraps over the end of data space (0xFFFF).
Refer to the specific device family reference manual for more information on the stack error trap.
0x0000
0xFFFE
0x0800
W14 (FP)
Parameter 1
W15 (SP)
TASKA
Frame
of
Parameter 2
Parameter 3
PC<15:0>
(1)
0:PC<22:16>
<TOS>
Note 1: In dsPIC33E/PIC24E devices, the SFA bit is stacked instead of
PC<0>
0x0000
0xFFFE
0x0800
W14 (FP)
Parameter 1
W15 (SP)
TASKA
Frame
of
Parameter 2
Parameter 3
PC<15:0>
(1)
0:PC<22:16>
<TOS>
FP of TASKA
Temp Word 1
Temp Word 2
Note 1: In dsPIC33E/PIC24E devices, the SFA bit is stacked instead of
PC<0>

- 1
- 2
…
- 72
- 73
- 74
- 75
- 76
…
- 501
- 502