# Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

### Protego

# PIC24FJ32MC10X -- Family Data Sheet

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© 2011-2012 Microchip Technology Inc. Preliminary DS39997C-page 7
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
Pin Diagrams (Continued)
36-Pin VTLA
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available
peripherals.
2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be
connected to V
SS externally.
3: The PWM Fault pins are enabled and asserted during any reset event. Refer to Section 15.2
“PWM Faults” for more information on the PWM faults.
N/C
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
MCLR
AVDD
PWM1L1/RP15
(1)
/CN11/RB15
PWM1H1/RTCC/RP14
(1)
/CN12/RB14
AVSS
N/C
N/C
V
SS
SDA1/SDI1/RP9
(1)
/CN21/RB9
PWM1L2/RP13
(1)
/CN13/RB13
PWM1H2/RP12
(1)
/CN14/RB12
PWM1H3/RP10
(1)
/CN16/RB10
PWM1L3/RP11
(1)
/CN15/RB11
VDD
VCAP
VDD
PGED1/AN2/C2INA/C1INC/RP0
(1)
/CN4/RB0
PGED3/SOSCI/RP4
(1)
/CN1/RB4
OSCO/CLKO/CN29/RA3
AN5/C3IND/C2IND/RP3
(1)
/CN7/RB3
AN4/C3INC/C2INC/RP2
(1)
/CN6/RB2
PGEC1/AN3/
CV
REFIN
/CV
REFOUT
/C2INB/C1IND/RP1
(1)
/CN5/RB1
VSS
OSCI/CLKI/CN30/RA2
N/C (Vss)
N/C
FLTB1
(3)
/ASDA1/RP5
(1)
/CN27/RB5
PGEC3/SOSCO/T1CK/CN0/RA4
FLTA1
(3)
/ASCL1/RP6
(1)
/CN24/RB6
SCK1/INT0/RP7
(1)
/CN23/RB7
SCL1/SDO1/RP8
(1)
/CN22/RB8
V
DD
N/C (VDD)
PIC24FJ16MC102
= Pins are up to 5V tolerant
1
10
33 32 31 30 29 28
2
3
4
5
6
24
23
22
21
20
19
11 12 13 14 15
7
8
9
34
35
36
16
17
18
27
26
25

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